| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | nvidia,tegra124-xusb-padctl.txt | 47 subnode that describes only an IDDQ parameter implies no information about
60 - nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)
69 The nvidia,iddq property does not apply to this group.
75 The nvidia,iddq property does not apply to this group.
119 nvidia,iddq = <0>;
126 nvidia,iddq = <0>;
132 nvidia,iddq = <0>;
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | tegra210-p2371-2180.dts | 44 nvidia,iddq = <0>;
50 nvidia,iddq = <0>;
56 nvidia,iddq = <0>;
63 nvidia,iddq = <0>;
69 nvidia,iddq = <0>;
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| H A D | tegra124-jetson-tk1.dts | 286 nvidia,iddq = <0>;
293 nvidia,iddq = <0>;
299 nvidia,iddq = <0>;
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| H A D | tegra124-cei-tk1-som.dts | 287 nvidia,iddq = <0>;
294 nvidia,iddq = <0>;
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| H A D | tegra124-apalis.dts | 1935 nvidia,iddq = <0>;
1942 nvidia,iddq = <0>;
1948 nvidia,iddq = <0>;
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| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | xusb-padctl-common.c | 110 group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1); in tegra_xusb_padctl_group_parse_dt()
178 * Set IDDQ if supported on the lane and specified in the in tegra_xusb_padctl_group_apply()
181 if (lane->iddq > 0 && group->iddq >= 0) { in tegra_xusb_padctl_group_apply()
182 if (group->iddq != 0) in tegra_xusb_padctl_group_apply()
183 value &= ~(1 << lane->iddq); in tegra_xusb_padctl_group_apply()
185 value |= 1 << lane->iddq; in tegra_xusb_padctl_group_apply()
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| H A D | xusb-padctl-common.h | 23 unsigned int iddq; member
46 int iddq; member
59 int iddq; member
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| H A D | cpu.c | 160 /* Disable IDDQ */ in pllx_set_iddq()
165 debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__, in pllx_set_iddq()
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| /openbmc/linux/drivers/pinctrl/tegra/ |
| H A D | pinctrl-tegra-xusb.c | 74 unsigned int iddq; member
146 { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
344 /* lanes with iddq == 0 don't support this parameter */ in tegra_xusb_padctl_pinconf_group_get()
345 if (lane->iddq == 0) in tegra_xusb_padctl_pinconf_group_get()
350 if (value & BIT(lane->iddq)) in tegra_xusb_padctl_pinconf_group_get()
387 /* lanes with iddq == 0 don't support this parameter */ in tegra_xusb_padctl_pinconf_group_set()
388 if (lane->iddq == 0) in tegra_xusb_padctl_pinconf_group_set()
394 regval &= ~BIT(lane->iddq); in tegra_xusb_padctl_pinconf_group_set()
396 regval |= BIT(lane->iddq); in tegra_xusb_padctl_pinconf_group_set()
836 .iddq = _iddq, \
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| /openbmc/phosphor-dbus-interfaces/yaml/com/ibm/ipzvpd/ |
| H A D | CRP0.interface.yaml | 31 IQ keyword.IDDQ (Chip Level, EX Level) data.
35 TC keyword.IDDQ (Chip Level, EX Level) data.
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| /openbmc/linux/arch/arm/mach-tegra/ |
| H A D | sleep-tegra30.S | 163 .macro pll_iddq_exit, rd, car, iddq, iddq_bit
164 ldr \rd, [\car, #\iddq]
166 str \rd, [\car, #\iddq]
169 .macro pll_iddq_entry, rd, car, iddq, iddq_bit
170 ldr \rd, [\car, #\iddq]
172 str \rd, [\car, #\iddq]
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| /openbmc/linux/drivers/phy/hisilicon/ |
| H A D | phy-hi3660-usb3.c | 102 /* exit from IDDQ mode */ in hi3660_phy_init()
108 /* delay for exit from IDDQ mode */ in hi3660_phy_init()
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| H A D | phy-hi3670-usb3.c | 483 /* Exit from IDDQ mode */ in hi3670_phy_init()
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-tegra210.c | 794 /* Defaults assert PLL reset, and set IDDQ */ in tegra210_pllcx_set_defaults()
844 pr_warn("PLL_A boot enabled with IDDQ set\n"); in tegra210_plla_set_defaults()
869 /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */ in tegra210_plla_set_defaults()
901 /* ignore lock, DSI and SDM controls, make sure IDDQ not set */ in tegra210_plld_set_defaults()
925 /* set IDDQ, enable lock detect, disable SDM */ in tegra210_plld_set_defaults()
951 pr_warn("plldss boot enabled with IDDQ set\n"); in plldss_defaults()
1003 /* set IDDQ, enable lock detect, configure SDM/SSC */ in plldss_defaults()
1083 /* The PLL doesn't work if it's in IDDQ. */ in tegra210_pllre_set_defaults()
1086 pr_warn("unexpected IDDQ bit set for enabled clock\n"); in tegra210_pllre_set_defaults()
1100 /* set IDDQ, enable lock detect */ in tegra210_pllre_set_defaults()
[all …]
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| H A D | clk.h | 228 * @iddq_reg: PLL IDDQ register offset
229 * @iddq_bit_idx: Bit index to enable PLL IDDQ
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| H A D | clk-pll.c | 924 * create falling edge on PLLE IDDQ input. in clk_plle_training()
2073 * configuring dynamic ramping and setting IDDQ in that path. in tegra_clk_register_pllxc()
2388 WARN(1, "%s is on but IDDQ set\n", name); in tegra_clk_register_pllss()
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| /openbmc/linux/drivers/soc/tegra/fuse/ |
| H A D | speedo-tegra210.c | 116 /* Read speedo/IDDQ fuses */ in tegra210_init_speedo_data()
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| /openbmc/linux/Documentation/networking/dsa/ |
| H A D | bcm_sf2.rst | 102 - putting integrated PHYs in IDDQ/low-power
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| /openbmc/linux/drivers/ata/ |
| H A D | ahci_tegra.c | 397 * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane in tegra_ahci_controller_init()
398 * IDDQ Signals in tegra_ahci_controller_init()
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | gk20a.c | 560 /* set IDDQ */ in gk20a_clk_fini()
572 /* get out from IDDQ */ in gk20a_clk_init()
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| H A D | gm20b.c | 737 /* set IDDQ */ in gm20b_clk_fini()
819 /* get out from IDDQ */ in gm20b_clk_init()
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| /openbmc/linux/drivers/phy/intel/ |
| H A D | phy-intel-keembay-usb.c | 95 dev_err(priv->dev, "error iddq disable: %d\n", ret); in keembay_usb_clocks_on()
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | xusb-padctl.c | 88 .iddq = _iddq, \
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra210/ |
| H A D | xusb-padctl.c | 68 .iddq = _iddq, \
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| /openbmc/u-boot/drivers/pci/ |
| H A D | pci_tegra.c | 677 /* override IDDQ to 1 on all 4 lanes */ in tegra_pcie_phy_enable()
710 /* turn off IDDQ override */ in tegra_pcie_phy_enable()
|