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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dxlnx,gmii-to-rgmii.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx GMII to RGMII Converter
10 - Harini Katakam <harini.katakam@amd.com>
13 The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media
14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
17 The Management Data Input/Output (MDIO) interface is used to configure the
20 The core cannot function without an external phy connected to it.
[all …]
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
22 LANs. It interfaces directly to twisted pair media via an external
23 transformer. This device interfaces directly to the MAC layer through the
25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
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H A Dcpsw.txt2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
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H A Dti,cpsw-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
16 gigabit media independent interface (GMII),reduced gigabit media
17 independent interface (RGMII), reduced media independent interface (RMII),
24 - const: ti,cpsw-switch
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H A Dsnps,dwc-qos-ethernet.txt3 This binding is deprecated, but it continues to be supported, but new
4 features should be preferably added to the stmmac binding document.
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
19 This combination is deprecated. It should be treated as equivalent to
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
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H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 provides connectivity to an external ethernet PHY supporting different
12 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
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H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
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H A Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
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H A Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
37 - description: main controller clock
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H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
22 Specifies the MAC address that was assigned to the network device.
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
31 to the device by the boot program is different from the
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H A Dibm,emac.txt4 the Axon bridge. To operate this needs to interact with a this
5 special McMAL DMA controller, and sometimes an RGMII or ZMII
6 interface. In addition to the nodes and properties described
8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-gmii-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
20 +--------------+
21 +-------------------------------+ |SCM |
22 | CPSW | | +---------+ |
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/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-helper-rgmii.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * Functions for RGMII/GMII/MII initialization, configuration,
39 * Probe RGMII ports and determine the number present
41 * @interface: Interface to probe
43 * Returns Number of RGMII/GMII/MII ports (0-4).
49 * Put an RGMII interface in loopback mode. Internal packets sent
53 * @port: IPD port number to loop.
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/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
16 This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
17 The port number is added to the minor number of the device. Unlike the
18 CPM UART driver, the port-number is required for the QE UART driver.
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/openbmc/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-rgmii.c7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Functions for RGMII/GMII/MII initialization, configuration,
34 #include <asm/octeon/cvmx-config.h>
36 #include <asm/octeon/cvmx-pko.h>
37 #include <asm/octeon/cvmx-helper.h>
38 #include <asm/octeon/cvmx-helper-board.h>
40 #include <asm/octeon/cvmx-npi-defs.h>
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H A Dcvmx-helper.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <asm/octeon/cvmx-config.h>
38 #include <asm/octeon/cvmx-fpa.h>
39 #include <asm/octeon/cvmx-pip.h>
40 #include <asm/octeon/cvmx-pko.h>
41 #include <asm/octeon/cvmx-ipd.h>
42 #include <asm/octeon/cvmx-spi.h>
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/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dethernet.txt1 The following properties are common to the Ethernet controllers:
3 - local-mac-address: array of 6 bytes, specifies the MAC address that was
4 assigned to the network device;
5 - mac-address: array of 6 bytes, specifies the MAC address that was last used by
6 the boot program; should be used in cases where the MAC address assigned to
7 the device by the boot program is different from the "local-mac-address"
9 - max-speed: number, specifies maximum speed in Mbit/s supported by the device;
10 - max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
12 - phy-mode: string, operation mode of the PHY interface; supported values are
13 "mii", "gmii", "sgmii", "qsgmii", "tbi", "rev-mii", "rmii", "rgmii", "rgmii-id",
[all …]
H A Dsnps,dwc-qos-ethernet.txt10 - compatible: One of:
11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
15 - "snps,dwc-qos-ethernet-4.10"
16 This combination is deprecated. It should be treated as equivalent to
17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
21 same order. See ../clock/clock-bindings.txt.
[all …]
/openbmc/u-boot/include/
H A Dphy_interface.h1 /* SPDX-License-Identifier: GPL-2.0+ */
42 [PHY_INTERFACE_MODE_GMII] = "gmii",
44 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
48 [PHY_INTERFACE_MODE_RGMII] = "rgmii",
49 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
50 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
51 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
58 [PHY_INTERFACE_MODE_25G_AUI] = "25g-aui",
62 [PHY_INTERFACE_MODE_NCSI] = "NC-SI",
68 /* Default to unknown */ in phy_string_for_interface()
H A Dfsl_dtsec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
30 u32 ipgifg; /* inter-packet/inter-frame gap */
31 u32 hafdup; /* half-duplex control */
47 u32 tr127; /* Tx and Rx 65 to 127 bytes frame */
48 u32 tr255; /* Tx and Rx 128 to 255 bytes frame */
49 u32 tr511; /* Tx and Rx 256 to 511 bytes frame */
50 u32 tr1k; /* Tx and Rx 512 to 1023 bytes frame */
51 u32 trmax; /* Tx and Rx 1024 to 1518 bytes frame */
52 u32 trmgv; /* Tx and Rx 1519 to 1522 good VLAN frame */
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-phydev6 Symbolic link to the network device this PHY device is
7 attached to.
16 a boolean. This information is provided to help troubleshooting
24 This attribute contains the 32-bit PHY Identifier as reported
26 This ID is used to match the device with the appropriate
36 This interface mode is used to configure the Ethernet MAC with the
37 appropriate mode for its data lines to the PHY hardware.
41 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
42 rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii
43 xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui,
[all …]
/openbmc/linux/arch/arm/boot/dts/gemini/
H A Dgemini-sq201.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
31 debounce-interval = <100>;
32 wakeup-source;
[all …]
H A Dgemini-nas4220b.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for the Gemini-based Raidsonic NAS IB-4220-B
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
12 model = "Raidsonic NAS IB-4220-B";
13 compatible = "raidsonic,ib-4220-b", "cortina,gemini";
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
[all …]
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-a20-gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
32 * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
33 * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
79 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
81 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
86 #define GMAC_RGSMIIIS 0x000000d8 /* RGMII/SMII status */
88 /* SGMII/RGMII status register */
105 #define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */
119 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
144 /* GMII ADDR defines */
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