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/openbmc/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c104 * Covers frequency and voltage settings of the DMC operating mode.
112 * struct exynos5_dmc - main structure describing DMC device
113 * @dev: DMC device
238 static int exynos5_counters_set_event(struct exynos5_dmc *dmc) in exynos5_counters_set_event() argument
242 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_set_event()
243 if (!dmc->counter[i]) in exynos5_counters_set_event()
245 ret = devfreq_event_set_event(dmc->counter[i]); in exynos5_counters_set_event()
252 static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc) in exynos5_counters_enable_edev() argument
256 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_enable_edev()
257 if (!dmc->counter[i]) in exynos5_counters_enable_edev()
[all …]
H A DKconfig17 This adds driver for Samsung Exynos5422 SoC DMC (Dynamic Memory
19 Frequency Scaling in DMC and DRAM. It also supports changing timings
H A DMakefile2 obj-$(CONFIG_EXYNOS5422_DMC) += exynos5422-dmc.o
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dmc.c34 * DOC: DMC Firmware Support
36 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
71 return i915->display.dmc.dmc; in i915_to_dmc()
82 * New DMC additions should not use this. This is used solely to remain
83 * compatible with systems that have not yet updated DMC blobs to use
149 /* 0x09 for DMC */
152 /* Includes the DMC specific header in dwords */
167 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
209 /* DMC container header length in dwords */
225 /* DMC binary header length */
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_exynos4.c27 #include <asm/arch/dmc.h>
51 static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc) in phy_control_reset() argument
55 &dmc->phycontrol1); in phy_control_reset()
57 &dmc->phycontrol1); in phy_control_reset()
60 &dmc->phycontrol0); in phy_control_reset()
62 &dmc->phycontrol0); in phy_control_reset()
66 static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip) in dmc_config_mrs() argument
76 &dmc->directcmd); in dmc_config_mrs()
80 static void dmc_init(struct exynos4_dmc *dmc) in dmc_init() argument
87 writel(mem.control1, &dmc->phycontrol1); in dmc_init()
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H A Ddmc_init_ddr3.c13 #include <asm/arch/dmc.h>
39 struct exynos5_dmc *dmc; in ddr3_mem_ctrl_init() local
45 dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl(); in ddr3_mem_ctrl_init()
75 &dmc->concontrol); in ddr3_mem_ctrl_init()
77 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
102 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
105 &dmc->concontrol); in ddr3_mem_ctrl_init()
108 writel(mem->iv_size, &dmc->ivcontrol); in ddr3_mem_ctrl_init()
110 writel(mem->memconfig, &dmc->memconfig0); in ddr3_mem_ctrl_init()
111 writel(mem->memconfig, &dmc->memconfig1); in ddr3_mem_ctrl_init()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/edac/
H A Ddmc-520.yaml4 $id: http://devicetree.org/schemas/edac/dmc-520.yaml#
7 title: ARM DMC-520 EDAC
13 DMC-520 node is defined to describe DRAM error detection and correction.
20 - const: brcm,dmc-520
21 - const: arm,dmc-520
56 dmc0: dmc@200000 {
57 compatible = "brcm,dmc-520", "arm,dmc-520";
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3368-dmc.txt4 The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
15 - compatible: "rockchip,rk3368-dmc"
54 #include <dt-bindings/memory/rk3368-dmc.h>
56 dmc: dmc@ff610000 {
58 compatible = "rockchip,rk3368-dmc";
63 &dmc {
H A Drockchip,rk3399-dmc.txt3 - compatible: "rockchip,rk3399-dmc", "syscon"
18 dmc: dmc {
20 compatible = "rockchip,rk3399-dmc";
35 &dmc {
H A Drockchip,rk3288-dmc.txt3 - compatible: "rockchip,rk3288-dmc", "syscon"
18 -logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-su…
113 dmc: dmc@ff610000 {
114 compatible = "rockchip,rk3288-dmc", "syscon";
132 &dmc {
/openbmc/linux/Documentation/admin-guide/perf/
H A Dthunderx2-pmu.rst6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
13 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
22 L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dsamsung,exynos5422-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
22 switch the DMC and memory frequency.
27 - const: samsung,exynos5422-dmc
62 - description: DMC internal performance event counters in DREX0
63 - description: DMC internal performance event counters in DREX1
112 compatible = "samsung,exynos5422-dmc";
H A Drockchip,rk3399-dmc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
15 - rockchip,rk3399-dmc
34 DMC regulator supply.
363 compatible = "rockchip,rk3399-dmc";
/openbmc/linux/include/soc/amlogic/
H A Dmeson_ddr_pmu.h35 u64 channel_cnt[MAX_CHANNEL_NUM]; /* To save a DMC bandwidth-monitor channel counter */
48 int dmc_nr; /* The number of dmc controller */
49 int chann_nr; /* The number of dmc bandwidth monitor channels */
/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml49 VDD_MIF |--- DMC (Dynamic Memory Controller)
93 VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
110 VDD_MIF |--- DMC (Dynamic Memory Controller)
225 bus-dmc {
287 dmc: bus-dmc {
303 interconnects = <&dmc>;
314 interconnects = <&leftbus &dmc>;
/openbmc/linux/drivers/net/ethernet/sun/
H A Dniu.h19 #define DMC 0x600000UL macro
1978 #define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)
1984 #define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)
1990 #define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)
1996 #define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)
2026 #define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)
2029 #define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)
2032 #define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)
2035 #define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)
2038 #define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)
[all …]
/openbmc/linux/drivers/cpufreq/
H A Ds5pv210-cpufreq.c194 * ch: DMC port number 0 or 1
207 pr_err("Cannot find DMC port\n"); in s5pv210_set_refresh()
536 /* Find current refresh counter and frequency each DMC */ in s5pv210_cpu_init()
599 * and DMC controller registers directly and remove static mappings in s5pv210_cpufreq_probe()
632 for_each_compatible_node(np, NULL, "samsung,s5pv210-dmc") { in s5pv210_cpufreq_probe()
633 id = of_alias_get_id(np, "dmc"); in s5pv210_cpufreq_probe()
635 dev_err(dev, "failed to get alias of dmc node '%pOFn'\n", np); in s5pv210_cpufreq_probe()
643 dev_err(dev, "failed to map dmc%d registers\n", id); in s5pv210_cpufreq_probe()
652 dev_err(dev, "failed to find dmc%d node\n", id); in s5pv210_cpufreq_probe()
/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Damlogic,g12-ddr-pmu.yaml27 - description: DMC bandwidth register space.
28 - description: DMC PLL register space.
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/tslib/
H A Dtslib_1.23.bb44 PACKAGECONFIG[dmc] = "--enable-dmc,--disable-dmc"
/openbmc/u-boot/arch/arm/dts/
H A Drk3368-lion-u-boot.dtsi28 &dmc {
41 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
/openbmc/linux/drivers/perf/
H A DKconfig166 in the DDR4 Memory Controller (DMC).
184 tristate "Enable PMU support for the ARM DMC-620 memory controller"
187 Support for PMU events monitoring on the ARM DMC-620 memory
/openbmc/linux/drivers/edac/
H A Ddmc520_edac.c4 * EDAC driver for DMC-520 memory controller.
25 /* DMC-520 registers */
43 /* DMC-520 types, masks and bitfields */
634 { .compatible = "arm,dmc-520", },
655 MODULE_DESCRIPTION("DMC-520 ECC driver");
/openbmc/linux/drivers/pmdomain/amlogic/
H A Dmeson-secure-pwrc.c102 /* DMC is for DDR PHY ana/dig and DMC, and should be always on */
103 SEC_PD(DMC, GENPD_FLAG_ALWAYS_ON),
/openbmc/linux/drivers/devfreq/
H A DKconfig133 tristate "ARM RK3399 DMC DEVFREQ Driver"
140 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
/openbmc/openbmc/poky/meta-yocto-bsp/lib/oeqa/runtime/cases/
H A Dparselogs-ignores-genericx86-64.txt6 Failed to load DMC firmware

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