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/openbmc/linux/arch/x86/kernel/acpi/
H A Dapei.c15 struct acpi_hest_ia_corrected *cmc; in arch_apei_enable_cmcff() local
18 cmc = (struct acpi_hest_ia_corrected *)hest_hdr; in arch_apei_enable_cmcff()
19 if (!cmc->enabled) in arch_apei_enable_cmcff()
27 if (!(cmc->flags & ACPI_HEST_FIRMWARE_FIRST) || in arch_apei_enable_cmcff()
28 !cmc->num_hardware_banks) in arch_apei_enable_cmcff()
33 mc_bank = (struct acpi_hest_ia_error_bank *)(cmc + 1); in arch_apei_enable_cmcff()
34 for (i = 0; i < cmc->num_hardware_banks; i++, mc_bank++) in arch_apei_enable_cmcff()
/openbmc/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850-enbw-cmc.dts3 * Device Tree for AM1808 EnBW CMC board
12 compatible = "enbw,cmc", "ti,da850";
13 model = "EnBW CMC";
H A DMakefile4 da850-enbw-cmc.dtb \
/openbmc/u-boot/tools/binman/test/
H A D043_intel-cmc.dts10 intel-cmc {
11 filename = "cmc.bin";
/openbmc/linux/Documentation/devicetree/bindings/arm/ti/
H A Dti,davinci.yaml23 - enbw,cmc # EnBW AM1808 based CMC board
/openbmc/linux/drivers/acpi/apei/
H A Dhest.c69 struct acpi_hest_ia_corrected *cmc; in hest_esrc_len() local
70 cmc = (struct acpi_hest_ia_corrected *)hest_hdr; in hest_esrc_len()
71 len = sizeof(*cmc) + cmc->num_hardware_banks * in hest_esrc_len()
/openbmc/u-boot/arch/x86/cpu/queensbay/
H A DKconfig39 default "cmc.bin"
49 The location of the CMC binary is determined by a strap. It must be
/openbmc/linux/Documentation/networking/devlink/
H A Dsfc.rst25 * - ``fw.mgmt.cmc``
28 control units, this is the CMC control unit's firmware version.
/openbmc/linux/arch/ia64/kernel/
H A Dmca.c350 #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */
392 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
418 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
459 * Inputs : sal_info_type (Type of error record MCA/CMC/CPE)
470 static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" }; in ia64_mca_log_sal_error_record()
709 * disable the cmc interrupt vector.
721 * enable the cmc interrupt vector.
1417 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH); in ia64_mca_cmc_int_handler()
1422 /* If we're being hit with CMC interrupts, we won't in ia64_mca_cmc_int_handler()
1424 * disable CMC interrupts on this processor now. in ia64_mca_cmc_int_handler()
[all …]
H A Dsalinfo.c80 "cmc",
120 * read data -> return the INIT/MCA/CMC/CPE record.
201 * interrupts before calling this code for CMC/CPE. MCA and INIT events are
H A Dmachine_kexec.c113 /* Mask CMC and Performance Monitor interrupts */ in ia64_machine_kexec()
/openbmc/linux/drivers/scsi/aic7xxx/
H A Daic79xx.reg688 * CMC Receive Message 0
735 * CMC Receive Message 1
780 * CMC Receive Message 2
819 * CMC Receive Message 3
857 * CMC Sequencer Byte Count
904 * CMC Split Status 0
950 * CMC Split Status 1
1188 * CMC PCI Status
2894 * CMC SCB Array Count
2895 * Number of bytes to transfer between CMC SCB memory and SCBRAM.
[all …]
/openbmc/u-boot/tools/binman/etype/
H A Dintel_cmc.py12 """Entry containing an Intel Chipset Micro Code (CMC) file
/openbmc/linux/drivers/iio/potentiometer/
H A Dmcp41010.c5 * Copyright (c) 2018 Chris Coffey <cmc@babblebit.net>
200 MODULE_AUTHOR("Chris Coffey <cmc@babblebit.net>");
/openbmc/linux/arch/arm/mach-davinci/
H A Dda8xx-dt.c22 "enbw,cmc",
/openbmc/linux/Documentation/devicetree/bindings/iio/potentiometer/
H A Dmicrochip,mcp41010.yaml10 - Chris Coffey <cmc@babblebit.net>
/openbmc/linux/drivers/net/ethernet/sfc/
H A Defx_devlink.h21 #define EFX_DEVLINK_INFO_VERSION_FW_MGMT_CMC "fw.mgmt.cmc"
/openbmc/u-boot/arch/x86/dts/
H A Du-boot.dtsi58 intel-cmc {
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dimx7ulp-scg-clock.yaml15 modules, and Core Mode Controller (CMC)1 blocks
H A Dimx7ulp-pcc-clock.yaml15 modules, and Core Mode Controller (CMC)1 blocks
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Dcache.json58 …LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying co…
64 …nse. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying co…
/openbmc/linux/Documentation/devicetree/bindings/arm/aspeed/
H A Daspeed.yaml89 - facebook,minerva-cmc
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A Dcache.json298 …LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying co…
304 …nse. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying co…
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A Dcache.json304 …LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying co…
310 …nse. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying co…
/openbmc/linux/arch/arm64/include/asm/
H A Dacpi.h167 * IA-32 Architecture Corrected Machine Check (CMC) Firmware-First mode

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