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/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/
H A Ddr_ste.c806 static void dr_ste_copy_mask_misc(char *mask, struct mlx5dr_match_misc *spec, bool clr) in dr_ste_copy_mask_misc() argument
808 spec->gre_c_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_c_present, clr); in dr_ste_copy_mask_misc()
809 spec->gre_k_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_k_present, clr); in dr_ste_copy_mask_misc()
810 spec->gre_s_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_s_present, clr); in dr_ste_copy_mask_misc()
811 spec->source_vhca_port = IFC_GET_CLR(fte_match_set_misc, mask, source_vhca_port, clr); in dr_ste_copy_mask_misc()
812 spec->source_sqn = IFC_GET_CLR(fte_match_set_misc, mask, source_sqn, clr); in dr_ste_copy_mask_misc()
814 spec->source_port = IFC_GET_CLR(fte_match_set_misc, mask, source_port, clr); in dr_ste_copy_mask_misc()
816 IFC_GET_CLR(fte_match_set_misc, mask, source_eswitch_owner_vhca_id, clr); in dr_ste_copy_mask_misc()
818 spec->outer_second_prio = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_prio, clr); in dr_ste_copy_mask_misc()
819 spec->outer_second_cfi = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_cfi, clr); in dr_ste_copy_mask_misc()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Dregs.h32 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
121 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
122 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
123 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
124 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
125 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
126 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
127 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
128 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
129 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igc/
H A Digc_regs.h132 #define IGC_CRCERRS 0x04000 /* CRC Error Count - R/clr */
133 #define IGC_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
134 #define IGC_RXERRC 0x0400C /* Receive Error Count - R/clr */
135 #define IGC_MPC 0x04010 /* Missed Packet Count - R/clr */
136 #define IGC_SCC 0x04014 /* Single Collision Count - R/clr */
137 #define IGC_ECOL 0x04018 /* Excessive Collision Count - R/clr */
138 #define IGC_MCC 0x0401C /* Multiple Collision Count - R/clr */
139 #define IGC_LATECOL 0x04020 /* Late Collision Count - R/clr */
140 #define IGC_COLC 0x04028 /* Collision Count - R/clr */
141 #define IGC_RERC 0x0402C /* Receive Error Count - R/clr */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igb/
H A De1000_regs.h21 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
30 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
187 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
188 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
189 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
190 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
191 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
192 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
193 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
194 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-quark/
H A Dmsg_port.h108 #define msg_port_generic_clrsetbits(type, port, reg, clr, set) \ argument
111 & ~(clr)) | (set))
113 #define msg_port_clrbits(port, reg, clr) \ argument
114 msg_port_generic_clrsetbits(normal, port, reg, clr, 0)
117 #define msg_port_clrsetbits(port, reg, clr, set) \ argument
118 msg_port_generic_clrsetbits(normal, port, reg, clr, set)
120 #define msg_port_alt_clrbits(port, reg, clr) \ argument
121 msg_port_generic_clrsetbits(alt, port, reg, clr, 0)
124 #define msg_port_alt_clrsetbits(port, reg, clr, set) \ argument
125 msg_port_generic_clrsetbits(alt, port, reg, clr, set)
[all …]
/openbmc/linux/include/trace/events/
H A Dthp.h40 TP_PROTO(unsigned long addr, unsigned long pte, unsigned long clr, unsigned long set),
41 TP_ARGS(addr, pte, clr, set),
45 __field(unsigned long, clr)
52 __entry->clr = clr;
57 …page update at addr 0x%lx and pte = 0x%lx clr = 0x%lx, set = 0x%lx", __entry->addr, __entry->pte, …
61 TP_PROTO(unsigned long addr, unsigned long pmd, unsigned long clr, unsigned long set),
62 TP_ARGS(addr, pmd, clr, set)
66 TP_PROTO(unsigned long addr, unsigned long pud, unsigned long clr, unsigned long set),
67 TP_ARGS(addr, pud, clr, set)
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dhardware.h9 #define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | (set)) argument
11 #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) argument
15 #define rk_clrsetreg(addr, clr, set) \ argument
16 writel(((clr) | (set)) << 16 | (set), addr)
17 #define rk_clrreg(addr, clr) writel((clr) << 16, addr) argument
/openbmc/qemu/hw/net/
H A De1000x_regs.h118 * R/clr - register is read only and is cleared when read
134 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
169 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
170 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
171 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
172 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
173 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
174 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
175 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
176 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
[all …]
/openbmc/linux/arch/m68k/math-emu/
H A Dfp_util.S70 2: clr.l %d0
99 clr.l %d1 | sign defaults to zero
109 clr.l (%a0)
116 clr.l (%a0)+
117 clr.l (%a0)+
118 clr.l (%a0)
142 clr.l (%a0) | low lword = 0
236 clr.b (%a0)
274 clr.l %d0
279 clr.w -(%a0)
[all …]
/openbmc/u-boot/board/samsung/odroid/
H A Dodroid.c103 unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc; in board_clock_init() local
159 clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) | in board_clock_init()
163 clrsetbits_le32(&clk->div_cpu0, clr, set); in board_clock_init()
175 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); in board_clock_init()
178 clrsetbits_le32(&clk->div_cpu1, clr, set); in board_clock_init()
231 clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) | in board_clock_init()
248 clrsetbits_le32(&clk->div_dmc0, clr, set); in board_clock_init()
255 clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) | in board_clock_init()
271 clrsetbits_le32(&clk->div_dmc1, clr, set); in board_clock_init()
278 clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) | in board_clock_init()
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Datafb_utils.h85 " lsr.l #1,%1 ; jcc 1f ; clr.b (%0)+\n" in fb_memclear()
86 "1: lsr.l #1,%1 ; jcc 1f ; clr.w (%0)+\n" in fb_memclear()
87 "1: lsr.l #1,%1 ; jcc 1f ; clr.l (%0)+\n" in fb_memclear()
88 "1: lsr.l #1,%1 ; jcc 1f ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
96 " lsr.l #1,%2 ; jcc 1f ; clr.b (%0)+ ; subq.w #1,%1\n" in fb_memclear()
98 " clr.w (%0)+ ; subq.w #2,%1 ; jra 2f\n" in fb_memclear()
100 " clr.w (%0)+ ; subq.w #2,%1\n" in fb_memclear()
102 " lsr.l #1,%1 ; jcc 3f ; clr.l (%0)+\n" in fb_memclear()
103 "3: lsr.l #1,%1 ; jcc 4f ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
105 "5: clr.l (%0)+; clr.l (%0)+ ; clr.l (%0)+ ; clr.l (%0)+\n" in fb_memclear()
[all …]
/openbmc/linux/arch/sparc/lib/
H A Dffs.S14 clr %o0
21 clr %o1 /* 2 */
25 1: clr %o2
31 clr %o3
34 clr %o4
40 clr %o5
/openbmc/linux/arch/m68k/ifpsp060/src/
H A Ditest.S81 clr.l TESTCTR(%a6)
91 clr.l TESTCTR(%a6)
101 clr.l TESTCTR(%a6)
111 clr.l TESTCTR(%a6)
121 clr.l TESTCTR(%a6)
132 clr.l TESTCTR(%a6)
142 clr.l TESTCTR(%a6)
169 clr.l %d1
181 clr.l IREGS+0x8(%a6)
182 clr.l IREGS+0xc(%a6)
[all …]
/openbmc/linux/Documentation/admin-guide/
H A Dmono.rst5 (in the form of .exe files) without the need to use the mono CLR
11 1) You MUST FIRST install the Mono CLR support, either by downloading
21 Once the Mono CLR support has been installed, just check that
50 # Register support for .NET CLR binaries
53 # the Mono CLR runtime (usually /usr/local/bin/mono
55 echo ':CLR:M::MZ::/usr/bin/mono:' > /proc/sys/fs/binfmt_misc/register
/openbmc/linux/arch/arm64/kvm/hyp/nvhe/
H A Dtimer-sr.c42 u64 clr = 0, set = 0; in __timer_enable_traps() local
49 clr = CNTHCTL_EL1PCEN; in __timer_enable_traps()
54 clr |= CNTHCTL_EL1PCTEN; in __timer_enable_traps()
57 clr <<= 10; in __timer_enable_traps()
61 sysreg_clear_set(cnthctl_el2, clr, set); in __timer_enable_traps()
/openbmc/linux/arch/m68k/ifpsp060/
H A Dos.S94 clr.l %d1 | return success
101 clr.l %d1 | return success
127 clr.l %d1 | return success
134 clr.l %d1 | return success
151 clr.l %d0 | clear whole longword
152 clr.l %d1 | assume success
187 clr.l %d1 | assume success
188 clr.l %d0 | clear whole longword
223 clr.l %d1 | assume success
245 clr.l %d1 | assume success
[all …]
/openbmc/u-boot/drivers/video/
H A Dconsole_rotate.c14 static int console_set_row_1(struct udevice *dev, uint row, int clr) in console_set_row_1() argument
30 *dst++ = clr; in console_set_row_1()
39 *dst++ = clr; in console_set_row_1()
48 *dst++ = clr; in console_set_row_1()
146 static int console_set_row_2(struct udevice *dev, uint row, int clr) in console_set_row_2() argument
161 *dst++ = clr; in console_set_row_2()
170 *dst++ = clr; in console_set_row_2()
179 *dst++ = clr; in console_set_row_2()
273 static int console_set_row_3(struct udevice *dev, uint row, int clr) in console_set_row_3() argument
288 *dst++ = clr; in console_set_row_3()
[all …]
/openbmc/linux/drivers/staging/media/omap4iss/
H A Diss.h187 * @clr: bit mask to be cleared
191 u32 offset, u32 clr) in iss_reg_clr() argument
195 iss_reg_write(iss, res, offset, v & ~clr); in iss_reg_clr()
219 * @clr: bit mask to be cleared
222 * Clear the clr mask first and then set the set mask.
226 u32 offset, u32 clr, u32 set) in iss_reg_update() argument
230 iss_reg_write(iss, res, offset, (v & ~clr) | set); in iss_reg_update()
/openbmc/linux/drivers/clocksource/
H A Dtimer-armada-370-xp.c88 static void local_timer_ctrl_clrset(u32 clr, u32 set) in local_timer_ctrl_clrset() argument
90 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, in local_timer_ctrl_clrset()
173 u32 clr = 0, set = 0; in armada_370_xp_timer_starting_cpu() local
178 clr = TIMER0_25MHZ; in armada_370_xp_timer_starting_cpu()
179 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_starting_cpu()
242 u32 clr = 0, set = 0; in armada_370_xp_timer_common_init() local
261 clr = TIMER0_25MHZ; in armada_370_xp_timer_common_init()
264 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); in armada_370_xp_timer_common_init()
265 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_common_init()
/openbmc/u-boot/drivers/net/
H A De1000.h686 * R/clr - register is read only and is cleared when read
701 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
770 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
771 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
772 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
773 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
774 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
775 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
776 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
777 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
[all …]
H A Dpic32_eth.c63 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_mii_init()
77 writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */ in pic32_mii_init()
83 writel(EMAC_RMII_RESET, &emac_p->supp.clr); in pic32_mii_init()
141 writel(EMAC_FULLDUP, &emac_p->cfg2.clr); in pic32_mac_adjust_link()
150 writel(EMAC_RMII_SPD100, &emac_p->supp.clr); in pic32_mac_adjust_link()
196 writel(EMAC_RMII_SPD100, &emac_p->supp.clr); in pic32_mac_init()
238 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_ctrl_reset()
248 writel(0xffffffff, &ectl_p->irq.clr); in pic32_ctrl_reset()
251 writel(0xffffffff, &ectl_p->txst.clr); in pic32_ctrl_reset()
252 writel(0xffffffff, &ectl_p->rxst.clr); in pic32_ctrl_reset()
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Ddcr-native.h112 unsigned clr, unsigned set) in __dcri_clrset() argument
120 val = (mfdcrx(base_data) & ~clr) | set; in __dcri_clrset()
124 val = (__mfdcr(base_data) & ~clr) | set; in __dcri_clrset()
138 #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ argument
140 reg, clr, set)
/openbmc/linux/arch/arm/mach-rpc/
H A Dirq.c14 #define CLR 0x04 macro
132 writeb(mask, base + CLR); in iomd_irq_mask_ack()
168 unsigned int irq, clr, set; in rpc_init_irq() local
181 clr = IRQ_NOREQUEST; in rpc_init_irq()
185 clr |= IRQ_NOPROBE; in rpc_init_irq()
195 irq_modify_status(irq, clr, set); in rpc_init_irq()
203 irq_modify_status(irq, clr, set); in rpc_init_irq()
211 irq_modify_status(irq, clr, set); in rpc_init_irq()
218 irq_modify_status(irq, clr, set); in rpc_init_irq()
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.h135 /* [31:16] RW intr_stat/clr. Default 0.
139 * [ 21] stat/clr of eof interrupt
141 * [ 19] stat/clr of de_rise interrupt
142 * [ 18] stat/clr of vs_fall interrupt
143 * [ 17] stat/clr of vs_rise interrupt
144 * [ 16] stat/clr of dwc_edpite interrupt
/openbmc/u-boot/common/
H A Dlcd_console_rotation.c31 static inline void console_setrow90(struct console_t *pcons, u32 row, int clr) in console_setrow90() argument
40 *dst-- = clr; in console_setrow90()
86 static inline void console_setrow180(struct console_t *pcons, u32 row, int clr) in console_setrow180() argument
94 *dst++ = clr; in console_setrow180()
133 static inline void console_setrow270(struct console_t *pcons, u32 row, int clr) in console_setrow270() argument
141 *dst++ = clr; in console_setrow270()

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