1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2faa83232SBin Meng /* 3faa83232SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4faa83232SBin Meng */ 5faa83232SBin Meng 6faa83232SBin Meng #ifndef _QUARK_MSG_PORT_H_ 7faa83232SBin Meng #define _QUARK_MSG_PORT_H_ 8faa83232SBin Meng 9faa83232SBin Meng /* 10faa83232SBin Meng * In the Quark SoC, some chipset commands are accomplished by utilizing 11faa83232SBin Meng * the internal message network within the host bridge (D0:F0). Accesses 12faa83232SBin Meng * to this network are accomplished by populating the message control 13faa83232SBin Meng * register (MCR), Message Control Register eXtension (MCRX) and the 14faa83232SBin Meng * message data register (MDR). 15faa83232SBin Meng */ 16faa83232SBin Meng #define MSG_CTRL_REG 0xd0 /* Message Control Register */ 17faa83232SBin Meng #define MSG_DATA_REG 0xd4 /* Message Data Register */ 18faa83232SBin Meng #define MSG_CTRL_EXT_REG 0xd8 /* Message Control Register EXT */ 19faa83232SBin Meng 20faa83232SBin Meng /* Normal Read/Write OpCodes */ 21faa83232SBin Meng #define MSG_OP_READ 0x10 22faa83232SBin Meng #define MSG_OP_WRITE 0x11 23faa83232SBin Meng 24faa83232SBin Meng /* Alternative Read/Write OpCodes */ 25faa83232SBin Meng #define MSG_OP_ALT_READ 0x06 26faa83232SBin Meng #define MSG_OP_ALT_WRITE 0x07 27faa83232SBin Meng 28faa83232SBin Meng /* IO Read/Write OpCodes */ 29faa83232SBin Meng #define MSG_OP_IO_READ 0x02 30faa83232SBin Meng #define MSG_OP_IO_WRITE 0x03 31faa83232SBin Meng 32faa83232SBin Meng /* All byte enables */ 33faa83232SBin Meng #define MSG_BYTE_ENABLE 0xf0 34faa83232SBin Meng 35faa83232SBin Meng #ifndef __ASSEMBLY__ 36faa83232SBin Meng 37faa83232SBin Meng /** 38faa83232SBin Meng * msg_port_setup - set up the message port control register 39faa83232SBin Meng * 40faa83232SBin Meng * @op: message bus access opcode 41faa83232SBin Meng * @port: port number on the message bus 42faa83232SBin Meng * @reg: register number within a port 43faa83232SBin Meng */ 44faa83232SBin Meng void msg_port_setup(int op, int port, int reg); 45faa83232SBin Meng 46faa83232SBin Meng /** 47faa83232SBin Meng * msg_port_read - read a message port register using normal opcode 48faa83232SBin Meng * 49faa83232SBin Meng * @port: port number on the message bus 50faa83232SBin Meng * @reg: register number within a port 51faa83232SBin Meng * 52faa83232SBin Meng * @return: message port register value 53faa83232SBin Meng */ 54faa83232SBin Meng u32 msg_port_read(u8 port, u32 reg); 55faa83232SBin Meng 56faa83232SBin Meng /** 57faa83232SBin Meng * msg_port_write - write a message port register using normal opcode 58faa83232SBin Meng * 59faa83232SBin Meng * @port: port number on the message bus 60faa83232SBin Meng * @reg: register number within a port 61faa83232SBin Meng * @value: register value to write 62faa83232SBin Meng */ 63faa83232SBin Meng void msg_port_write(u8 port, u32 reg, u32 value); 64faa83232SBin Meng 65faa83232SBin Meng /** 66faa83232SBin Meng * msg_port_alt_read - read a message port register using alternative opcode 67faa83232SBin Meng * 68faa83232SBin Meng * @port: port number on the message bus 69faa83232SBin Meng * @reg: register number within a port 70faa83232SBin Meng * 71faa83232SBin Meng * @return: message port register value 72faa83232SBin Meng */ 73faa83232SBin Meng u32 msg_port_alt_read(u8 port, u32 reg); 74faa83232SBin Meng 75faa83232SBin Meng /** 76faa83232SBin Meng * msg_port_alt_write - write a message port register using alternative opcode 77faa83232SBin Meng * 78faa83232SBin Meng * @port: port number on the message bus 79faa83232SBin Meng * @reg: register number within a port 80faa83232SBin Meng * @value: register value to write 81faa83232SBin Meng */ 82faa83232SBin Meng void msg_port_alt_write(u8 port, u32 reg, u32 value); 83faa83232SBin Meng 84faa83232SBin Meng /** 85faa83232SBin Meng * msg_port_io_read - read a message port register using I/O opcode 86faa83232SBin Meng * 87faa83232SBin Meng * @port: port number on the message bus 88faa83232SBin Meng * @reg: register number within a port 89faa83232SBin Meng * 90faa83232SBin Meng * @return: message port register value 91faa83232SBin Meng */ 92faa83232SBin Meng u32 msg_port_io_read(u8 port, u32 reg); 93faa83232SBin Meng 94faa83232SBin Meng /** 95faa83232SBin Meng * msg_port_io_write - write a message port register using I/O opcode 96faa83232SBin Meng * 97faa83232SBin Meng * @port: port number on the message bus 98faa83232SBin Meng * @reg: register number within a port 99faa83232SBin Meng * @value: register value to write 100faa83232SBin Meng */ 101faa83232SBin Meng void msg_port_io_write(u8 port, u32 reg, u32 value); 102faa83232SBin Meng 103d0b3e3bfSBin Meng /* clrbits, setbits, clrsetbits macros for message port access */ 104d0b3e3bfSBin Meng 105d0b3e3bfSBin Meng #define msg_port_normal_read msg_port_read 106d0b3e3bfSBin Meng #define msg_port_normal_write msg_port_write 107d0b3e3bfSBin Meng 108d0b3e3bfSBin Meng #define msg_port_generic_clrsetbits(type, port, reg, clr, set) \ 109d0b3e3bfSBin Meng msg_port_##type##_write(port, reg, \ 110d0b3e3bfSBin Meng (msg_port_##type##_read(port, reg) \ 111d0b3e3bfSBin Meng & ~(clr)) | (set)) 112d0b3e3bfSBin Meng 113d0b3e3bfSBin Meng #define msg_port_clrbits(port, reg, clr) \ 114d0b3e3bfSBin Meng msg_port_generic_clrsetbits(normal, port, reg, clr, 0) 115d0b3e3bfSBin Meng #define msg_port_setbits(port, reg, set) \ 116d0b3e3bfSBin Meng msg_port_generic_clrsetbits(normal, port, reg, 0, set) 117d0b3e3bfSBin Meng #define msg_port_clrsetbits(port, reg, clr, set) \ 118d0b3e3bfSBin Meng msg_port_generic_clrsetbits(normal, port, reg, clr, set) 119d0b3e3bfSBin Meng 120d0b3e3bfSBin Meng #define msg_port_alt_clrbits(port, reg, clr) \ 121d0b3e3bfSBin Meng msg_port_generic_clrsetbits(alt, port, reg, clr, 0) 122d0b3e3bfSBin Meng #define msg_port_alt_setbits(port, reg, set) \ 123d0b3e3bfSBin Meng msg_port_generic_clrsetbits(alt, port, reg, 0, set) 124d0b3e3bfSBin Meng #define msg_port_alt_clrsetbits(port, reg, clr, set) \ 125d0b3e3bfSBin Meng msg_port_generic_clrsetbits(alt, port, reg, clr, set) 126d0b3e3bfSBin Meng 127d0b3e3bfSBin Meng #define msg_port_io_clrbits(port, reg, clr) \ 128d0b3e3bfSBin Meng msg_port_generic_clrsetbits(io, port, reg, clr, 0) 129d0b3e3bfSBin Meng #define msg_port_io_setbits(port, reg, set) \ 130d0b3e3bfSBin Meng msg_port_generic_clrsetbits(io, port, reg, 0, set) 131d0b3e3bfSBin Meng #define msg_port_io_clrsetbits(port, reg, clr, set) \ 132d0b3e3bfSBin Meng msg_port_generic_clrsetbits(io, port, reg, clr, set) 133d0b3e3bfSBin Meng 134faa83232SBin Meng #endif /* __ASSEMBLY__ */ 135faa83232SBin Meng 136faa83232SBin Meng #endif /* _QUARK_MSG_PORT_H_ */ 137