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Searched full:clk_top_spi_sel (Results 1 – 25 of 28) sorted by relevance

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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dmediatek,spi-mt65xx.yaml108 <&topckgen CLK_TOP_SPI_SEL>,
/openbmc/linux/include/dt-bindings/clock/
H A Dmt7986-clk.h51 #define CLK_TOP_SPI_SEL 28 macro
H A Dmt8135-clk.h87 #define CLK_TOP_SPI_SEL 76 macro
H A Dmediatek,mt7981-clk.h91 #define CLK_TOP_SPI_SEL 78 macro
H A Dmt8516-clk.h189 #define CLK_TOP_SPI_SEL 157 macro
H A Dmediatek,mt6795-clk.h100 #define CLK_TOP_SPI_SEL 89 macro
H A Dmt8173-clk.h102 #define CLK_TOP_SPI_SEL 92 macro
H A Dmt6765-clk.h142 #define CLK_TOP_SPI_SEL 107 macro
H A Dmediatek,mt8365-clk.h80 #define CLK_TOP_SPI_SEL 70 macro
H A Dmt2712-clk.h139 #define CLK_TOP_SPI_SEL 108 macro
H A Dmt8192-clk.h34 #define CLK_TOP_SPI_SEL 22 macro
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi557 <&topckgen CLK_TOP_SPI_SEL>,
636 <&topckgen CLK_TOP_SPI_SEL>,
649 <&topckgen CLK_TOP_SPI_SEL>,
662 <&topckgen CLK_TOP_SPI_SEL>,
675 <&topckgen CLK_TOP_SPI_SEL>,
H A Dmt8192.dtsi785 <&topckgen CLK_TOP_SPI_SEL>,
810 <&topckgen CLK_TOP_SPI_SEL>,
824 <&topckgen CLK_TOP_SPI_SEL>,
838 <&topckgen CLK_TOP_SPI_SEL>,
852 <&topckgen CLK_TOP_SPI_SEL>,
866 <&topckgen CLK_TOP_SPI_SEL>,
880 <&topckgen CLK_TOP_SPI_SEL>,
894 <&topckgen CLK_TOP_SPI_SEL>,
H A Dmt8516.dtsi391 <&topckgen CLK_TOP_SPI_SEL>,
H A Dmt7986a.dtsi309 <&topckgen CLK_TOP_SPI_SEL>,
H A Dmt8365.dtsi482 <&topckgen CLK_TOP_SPI_SEL>,
H A Dmt8173.dtsi762 <&topckgen CLK_TOP_SPI_SEL>,
785 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7986-topckgen.c179 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
H A Dclk-mt7981-topckgen.c296 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
H A Dclk-mt8135.c374 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
H A Dclk-mt6795-topckgen.c467 TOP_MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x60, 16, 3, 23, 0),
H A Dclk-mt8173-topckgen.c546 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
H A Dclk-mt8516.c423 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
H A Dclk-mt8167.c612 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
H A Dclk-mt8365.c431 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060,

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