108727dd7SLeilk Liu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 208727dd7SLeilk Liu%YAML 1.2 308727dd7SLeilk Liu--- 408727dd7SLeilk Liu$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml# 508727dd7SLeilk Liu$schema: http://devicetree.org/meta-schemas/core.yaml# 608727dd7SLeilk Liu 708727dd7SLeilk Liutitle: SPI Bus controller for MediaTek ARM SoCs 808727dd7SLeilk Liu 908727dd7SLeilk Liumaintainers: 1008727dd7SLeilk Liu - Leilk Liu <leilk.liu@mediatek.com> 1108727dd7SLeilk Liu 1208727dd7SLeilk LiuallOf: 13*99a7fa0eSKrzysztof Kozlowski - $ref: /schemas/spi/spi-controller.yaml# 1408727dd7SLeilk Liu 1508727dd7SLeilk Liuproperties: 1608727dd7SLeilk Liu compatible: 1708727dd7SLeilk Liu oneOf: 1808727dd7SLeilk Liu - items: 1908727dd7SLeilk Liu - enum: 2008727dd7SLeilk Liu - mediatek,mt7629-spi 21901fc8e8SFabien Parent - mediatek,mt8365-spi 2208727dd7SLeilk Liu - const: mediatek,mt7622-spi 2308727dd7SLeilk Liu - items: 2408727dd7SLeilk Liu - enum: 2508727dd7SLeilk Liu - mediatek,mt8516-spi 2608727dd7SLeilk Liu - const: mediatek,mt2712-spi 2708727dd7SLeilk Liu - items: 2808727dd7SLeilk Liu - enum: 2908727dd7SLeilk Liu - mediatek,mt6779-spi 30ccbc5d0aSLeilk Liu - mediatek,mt8186-spi 3108727dd7SLeilk Liu - mediatek,mt8192-spi 3208727dd7SLeilk Liu - mediatek,mt8195-spi 3308727dd7SLeilk Liu - const: mediatek,mt6765-spi 3408727dd7SLeilk Liu - items: 3508727dd7SLeilk Liu - enum: 36da40a352SLeilk Liu - mediatek,mt7986-spi-ipm 370ee0ab0bSJohnson Wang - mediatek,mt8188-spi-ipm 38da40a352SLeilk Liu - const: mediatek,spi-ipm 39da40a352SLeilk Liu - items: 40da40a352SLeilk Liu - enum: 4108727dd7SLeilk Liu - mediatek,mt2701-spi 4208727dd7SLeilk Liu - mediatek,mt2712-spi 4308727dd7SLeilk Liu - mediatek,mt6589-spi 4408727dd7SLeilk Liu - mediatek,mt6765-spi 4508727dd7SLeilk Liu - mediatek,mt6893-spi 4608727dd7SLeilk Liu - mediatek,mt7622-spi 4708727dd7SLeilk Liu - mediatek,mt8135-spi 4808727dd7SLeilk Liu - mediatek,mt8173-spi 4908727dd7SLeilk Liu - mediatek,mt8183-spi 5008727dd7SLeilk Liu 5108727dd7SLeilk Liu reg: 5208727dd7SLeilk Liu maxItems: 1 5308727dd7SLeilk Liu 5408727dd7SLeilk Liu interrupts: 5508727dd7SLeilk Liu maxItems: 1 5608727dd7SLeilk Liu 5708727dd7SLeilk Liu clocks: 58a4765dfbSLeilk Liu minItems: 3 5908727dd7SLeilk Liu items: 6008727dd7SLeilk Liu - description: clock used for the parent clock 6108727dd7SLeilk Liu - description: clock used for the muxes clock 6208727dd7SLeilk Liu - description: clock used for the clock gate 63a4765dfbSLeilk Liu - description: clock used for the AHB bus, this clock is optional 6408727dd7SLeilk Liu 6508727dd7SLeilk Liu clock-names: 66a4765dfbSLeilk Liu minItems: 3 6708727dd7SLeilk Liu items: 6808727dd7SLeilk Liu - const: parent-clk 6908727dd7SLeilk Liu - const: sel-clk 7008727dd7SLeilk Liu - const: spi-clk 71a4765dfbSLeilk Liu - const: hclk 7208727dd7SLeilk Liu 7308727dd7SLeilk Liu mediatek,pad-select: 7408727dd7SLeilk Liu $ref: /schemas/types.yaml#/definitions/uint32-array 75d149dd2aSRob Herring minItems: 1 7608727dd7SLeilk Liu maxItems: 4 7708727dd7SLeilk Liu items: 7808727dd7SLeilk Liu enum: [0, 1, 2, 3] 7908727dd7SLeilk Liu description: 8008727dd7SLeilk Liu specify which pins group(ck/mi/mo/cs) spi controller used. 8108727dd7SLeilk Liu This is an array. 8208727dd7SLeilk Liu 8308727dd7SLeilk Liurequired: 8408727dd7SLeilk Liu - compatible 8508727dd7SLeilk Liu - reg 8608727dd7SLeilk Liu - interrupts 8708727dd7SLeilk Liu - clocks 8808727dd7SLeilk Liu - clock-names 8908727dd7SLeilk Liu - '#address-cells' 9008727dd7SLeilk Liu - '#size-cells' 9108727dd7SLeilk Liu 9208727dd7SLeilk LiuunevaluatedProperties: false 9308727dd7SLeilk Liu 9408727dd7SLeilk Liuexamples: 9508727dd7SLeilk Liu - | 9608727dd7SLeilk Liu #include <dt-bindings/clock/mt8173-clk.h> 9708727dd7SLeilk Liu #include <dt-bindings/gpio/gpio.h> 9808727dd7SLeilk Liu #include <dt-bindings/interrupt-controller/arm-gic.h> 9908727dd7SLeilk Liu #include <dt-bindings/interrupt-controller/irq.h> 10008727dd7SLeilk Liu 10108727dd7SLeilk Liu spi@1100a000 { 10208727dd7SLeilk Liu compatible = "mediatek,mt8173-spi"; 10308727dd7SLeilk Liu #address-cells = <1>; 10408727dd7SLeilk Liu #size-cells = <0>; 10508727dd7SLeilk Liu reg = <0x1100a000 0x1000>; 10608727dd7SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 10708727dd7SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 10808727dd7SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 10908727dd7SLeilk Liu <&pericfg CLK_PERI_SPI0>; 11008727dd7SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 11108727dd7SLeilk Liu cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>; 11208727dd7SLeilk Liu mediatek,pad-select = <1>, <0>; 11308727dd7SLeilk Liu }; 114