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Searched full:clk_apmixed_msdcpll (Results 1 – 25 of 33) sorted by relevance

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/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8186-apmixedsys.c61 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0,
132 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x0118),
H A Dclk-mt8192-apmixedsys.c79 PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000,
141 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
H A Dclk-mt6795-apmixedsys.c54 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
106 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
H A Dclk-mt8173-apmixedsys.c71 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
125 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
H A Dclk-mt8195-apmixedsys.c68 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
159 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
H A Dclk-mt8135-apmixedsys.c43 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
H A Dclk-mt8188-apmixedsys.c63 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
H A Dclk-mt2712-apmixedsys.c96 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
H A Dclk-mt8365-apmixedsys.c91 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22,
H A Dclk-mt8183-apmixedsys.c129 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0,
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c52 PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0,
139 FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
140 FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
141 FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4),
142 FACTOR0(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, 8),
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8186-fhctl.yaml56 clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
/openbmc/linux/include/dt-bindings/clock/
H A Dmt8135-clk.h113 #define CLK_APMIXED_MSDCPLL 6 macro
H A Dmt6797-clk.h111 #define CLK_APMIXED_MSDCPLL 4 macro
H A Dmediatek,mt6795-clk.h145 #define CLK_APMIXED_MSDCPLL 4 macro
H A Dmt8173-clk.h161 #define CLK_APMIXED_MSDCPLL 6 macro
H A Dmt6765-clk.h17 #define CLK_APMIXED_MSDCPLL 7 macro
H A Dmediatek,mt8365-clk.h235 #define CLK_APMIXED_MSDCPLL 4 macro
H A Dmt2712-clk.h20 #define CLK_APMIXED_MSDCPLL 8 macro
H A Dmt8183-clk.h16 #define CLK_APMIXED_MSDCPLL 5 macro
H A Dmt8186-clk.h269 #define CLK_APMIXED_MSDCPLL 5 macro
H A Dmt6779-clk.h172 #define CLK_APMIXED_MSDCPLL 7 macro
H A Dmt2701-clk.h179 #define CLK_APMIXED_MSDCPLL 5 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7623-clk.h181 #define CLK_APMIXED_MSDCPLL 4 macro
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6795-sony-xperia-m5.dts56 <&apmixedsys CLK_APMIXED_MSDCPLL>;

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