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/openbmc/openbmc/meta-ibm/recipes-phosphor/power/power-sequencer/swift/
H A Ducd90160.yaml1 - Device:
3 # Linux sysfs path for this power sequencer (0xC8 8-bit address)
4 path: /sys/bus/i2c/devices/i2c-8/8-0064
6 - "12.0V"
7 - "3.3V"
8 - "1.8V"
9 - "1.1V"
10 - "0.8V_SW"
11 - "5.0V"
12 - "VDN0"
[all …]
/openbmc/qemu/target/s390x/
H A Dgdbstub.c4 * Copyright (c) 2003-2005 Fabrice Bellard
22 #include "cpu.h"
23 #include "s390x-internal.h"
24 #include "exec/exec-all.h"
39 return gdb_get_regl(mem_buf, env->psw.addr); in s390_cpu_gdb_read_register()
41 return gdb_get_regl(mem_buf, env->regs[n - S390_R0_REGNUM]); in s390_cpu_gdb_read_register()
53 s390_cpu_set_psw(env, tmpl, env->psw.addr); in s390_cpu_gdb_write_register()
56 env->psw.addr = tmpl; in s390_cpu_gdb_write_register()
59 env->regs[n - S390_R0_REGNUM] = tmpl; in s390_cpu_gdb_write_register()
64 return 8; in s390_cpu_gdb_write_register()
[all …]
/openbmc/linux/tools/power/x86/intel-speed-select/
H A Disst-core-mbox.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Speed Select -- Enumerate and control features for Mailbox Interface
34 snprintf(level_str, sizeof(level_str), "level-%d", level); in mbox_get_trl_level_name()
66 if (id->cpu < 0) in mbox_is_punit_valid()
69 if (id->pkg < 0 || id->die < 0 || id->punit) in mbox_is_punit_valid()
75 static int _send_mmio_command(unsigned int cpu, unsigned int reg, int write, in _send_mmio_command() argument
84 debug_printf("mmio_cmd cpu:%d reg:%d write:%d\n", cpu, reg, write); in _send_mmio_command()
88 err(-1, "%s open failed", pathname); in _send_mmio_command()
91 io_regs.io_reg[0].logical_cpu = cpu; in _send_mmio_command()
101 if (ioctl(fd, cmd, &io_regs) == -1) { in _send_mmio_command()
[all …]
/openbmc/qemu/accel/tcg/
H A Dcputlb.c2 * Common CPU TLB handling
21 #include "qemu/main-loop.h"
22 #include "hw/core/tcg-cpu-ops.h"
23 #include "exec/exec-all.h"
24 #include "exec/page-protection.h"
28 #include "exec/tb-flush.h"
29 #include "exec/memory-internal.h"
31 #include "exec/mmu-access-type.h"
32 #include "exec/tlb-common.h"
35 #include "qemu/error-report.h"
[all …]
H A Dldst_atomicity.c.inc6 * SPDX-License-Identifier: GPL-2.0-or-later
9 * See the COPYING file in the top-level directory.
12 #include "host/load-extract-al16-al8.h.inc"
13 #include "host/store-insert-al16.h.inc"
20 #define HAVE_al8_fast (ATOMIC_REG_SIZE >= 8)
27 * examined separately for atomicity, return -lg2.
29 static int required_atomicity(CPUState *cpu, uintptr_t p, MemOp memop)
33 MemOp half = size ? size - 1 : 0;
47 tmp = (1 << size) - 1;
68 * One of the pair crosses the boundary, and is non-atomic.
[all …]
/openbmc/qemu/target/i386/hvf/
H A Dx86.c21 #include "cpu.h"
33 if (!var->p) {
38 ar = var->type & 15;
39 ar |= (var->s & 1) << 4;
40 ar |= (var->dpl & 3) << 5;
41 ar |= (var->p & 1) << 7;
42 ar |= (var->avl & 1) << 12;
43 ar |= (var->l & 1) << 13;
44 ar |= (var->db & 1) << 14;
45 ar |= (var->g & 1) << 15;
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dsmp-bmips.c20 #include <linux/cpu.h>
40 #include <asm/cpu-features.h>
53 static void bmips_set_reset_vec(int cpu, u32 val);
59 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
63 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
64 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
72 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) argument
73 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
74 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
75 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) argument
[all …]
/openbmc/qemu/hw/ppc/
H A Dpnv_core.c2 * QEMU PowerPC PowerNV CPU Core model
25 #include "target/ppc/cpu.h"
32 #include "hw/qdev-properties.h"
38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); in pnv_core_cpu_typename()
45 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) in pnv_core_cpu_reset() argument
47 CPUState *cs = CPU(cpu); in pnv_core_cpu_reset()
48 CPUPPCState *env = &cpu->env; in pnv_core_cpu_reset()
49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_reset()
57 env->gpr[3] = PNV_FDT_ADDR; in pnv_core_cpu_reset()
58 env->nip = 0x10; in pnv_core_cpu_reset()
[all …]
/openbmc/linux/Documentation/ABI/stable/
H A Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/dscr_default
2 Date: 13-May-2014
6 /sys/devices/system/cpu/cpuN/dscr on all CPUs.
9 all per-CPU defaults at the same time.
12 What: /sys/devices/system/cpu/cpu[0-9]+/dscr
13 Date: 13-May-2014
17 a CPU.
22 on any CPU where it executes (overriding the value described
27 What: /sys/devices/system/cpu/cpuX/topology/physical_package_id
33 What: /sys/devices/system/cpu/cpuX/topology/die_id
[all …]
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-t7.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <0x2>;
15 #size-cells = <0x0>;
17 cpu-map {
20 cpu = <&cpu100>;
23 cpu = <&cpu101>;
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroidhc1.dts1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include "exynos5422-odroid-core.dtsi"
16 compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \
19 led-controller {
20 compatible = "pwm-leds";
22 led-1 {
26 pwm-names = "pwm2";
27 max-brightness = <255>;
[all …]
H A Dexynos5422-odroidxu3-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
12 #include <dt-bindings/input/input.h>
13 #include "exynos5422-odroid-core.dtsi"
20 gpio-keys {
21 compatible = "gpio-keys";
22 pinctrl-names = "default";
23 pinctrl-0 = <&power_key>;
25 power-key {
36 debounce-interval = <0>;
[all …]
/openbmc/qemu/hw/intc/
H A Darm_gic.c4 * Copyright (c) 2006-2007 CodeSourcery.
11 * controller, MPCore distributed interrupt controller and ARMv7-M
26 #include "hw/core/cpu.h"
61 if (!qtest_enabled() && s->num_cpu > 1) { in gic_get_current_cpu()
62 return current_cpu->cpu_index; in gic_get_current_cpu()
77 return s->revision == 2 || s->security_extn; in gic_has_groups()
80 static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs) in gic_cpu_ns_access() argument
82 return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure; in gic_cpu_ns_access()
85 static inline void gic_get_best_irq(GICState *s, int cpu, in gic_get_best_irq() argument
89 int cm = 1 << cpu; in gic_get_best_irq()
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/openbmc/linux/tools/perf/util/
H A Dsvghelper.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * svghelper.c - helper functions for outputting svg
43 static double cpu2slot(int cpu) in cpu2slot() argument
45 return 2 * cpu + 1; in cpu2slot()
50 static double cpu2y(int cpu) in cpu2y() argument
53 return cpu2slot(topology_map[cpu]) * SLOT_MULT; in cpu2y()
55 return cpu2slot(cpu) * SLOT_MULT; in cpu2y()
62 X = 1.0 * svg_page_width * (__time - first_time) / (last_time - first_time); in time2pixels()
77 while (loop--) { in round_text_size()
102 new_width = (last_time - first_time) / 5000000; in open_svg()
[all …]
H A Daffinity.c1 // SPDX-License-Identifier: GPL-2.0
14 int sz = cpu__max_cpu().cpu + 8 - 1; in get_cpu_set_size()
21 return sz / 8; in get_cpu_set_size()
28 a->orig_cpus = bitmap_zalloc(cpu_set_size * 8); in affinity__setup()
29 if (!a->orig_cpus) in affinity__setup()
30 return -1; in affinity__setup()
31 sched_getaffinity(0, cpu_set_size, (cpu_set_t *)a->orig_cpus); in affinity__setup()
32 a->sched_cpus = bitmap_zalloc(cpu_set_size * 8); in affinity__setup()
33 if (!a->sched_cpus) { in affinity__setup()
34 zfree(&a->orig_cpus); in affinity__setup()
[all …]
/openbmc/linux/arch/x86/kernel/
H A Dmsr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ----------------------------------------------------------------------- *
4 * Copyright 2000-2008 H. Peter Anvin - All Rights Reserved
7 * ----------------------------------------------------------------------- */
13 * and then read/write in chunks of 8 bytes. A larger size means multiple
16 * This driver uses /dev/cpu/%d/msr where %d is the minor number, and on
17 * an SMP box will direct the access to CPU %d.
33 #include <linux/cpu.h>
58 int cpu = iminor(file_inode(file)); in msr_read() local
62 if (count % 8) in msr_read()
[all …]
H A Dhead_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
21 #include <asm/processor-flags.h>
26 #include <asm/nospec-branch.h>
33 * because we need identity-mapped pages.
36 #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
49 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
70 leaq (__end_init_task - PTREGS_SIZE)(%rip), %rsp
95 * be done now, since this also includes setup of the SEV-SNP CPUID table,
103 /* Sanitize CPU configuration */
[all …]
/openbmc/qemu/target/i386/
H A Dgdbstub.c4 * Copyright (c) 2003-2005 Fabrice Bellard
21 #include "accel/tcg/vcpu-state.h"
22 #include "cpu.h"
26 #include "linux-user/qemu.h"
32 8, 9, 10, 11, 12, 13, 14, 15
37 static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
41 * gdb_num_core_regs in target/i386/cpu.c
50 * general regs -----> 8 or 16
58 * fpu regs ----------> 8 or 16
62 * total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66
[all …]
/openbmc/linux/drivers/clk/mvebu/
H A Ddove.c1 // SPDX-License-Identifier: GPL-2.0
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
14 #include <linux/clk-provider.h>
18 #include "dove-divider.h"
23 * Dove PLL sample-at-reset configuration
25 * SAR0[8:5] : CPU frequency
29 * 8 = 800 MHz
39 * SAR0[11:9] : CPU to L2 Clock divider ratio
40 * 0 = (1/1) * CPU
41 * 2 = (1/2) * CPU
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c18 * <http://www.gnu.org/licenses/gpl-2.0.html>
23 #include "cpu.h"
26 #include "hw/qdev-properties.h"
29 #include "cpu-features.h"
34 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a35_initfn() local
36 cpu->dtb_compatible = "arm,cortex-a35"; in aarch64_a35_initfn()
37 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a35_initfn()
38 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a35_initfn()
39 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a35_initfn()
40 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a35_initfn()
[all …]
/openbmc/linux/arch/x86/kernel/cpu/
H A Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Routines to identify caches on Intel CPU.
7 * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
13 #include <linux/cpu.h>
28 #include "cpu.h"
60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-wa
388 amd_l3_disable_index(struct amd_northbridge * nb,int cpu,unsigned slot,unsigned long idx) amd_l3_disable_index() argument
428 amd_set_l3_disable_slot(struct amd_northbridge * nb,int cpu,unsigned slot,unsigned long index) amd_set_l3_disable_slot() argument
455 int cpu, err = 0; store_cache_disable() local
492 int cpu = cpumask_first(&this_leaf->shared_cpu_map); subcaches_show() local
502 int cpu = cpumask_first(&this_leaf->shared_cpu_map); subcaches_store() local
664 cacheinfo_amd_init_llc_id(struct cpuinfo_x86 * c,int cpu) cacheinfo_amd_init_llc_id() argument
702 cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 * c,int cpu) cacheinfo_hygon_init_llc_id() argument
744 unsigned int cpu = c->cpu_index; init_intel_cacheinfo() local
890 __cache_amd_cpumap_setup(unsigned int cpu,int index,struct _cpuid4_info_regs * base) __cache_amd_cpumap_setup() argument
947 __cache_cpumap_setup(unsigned int cpu,int index,struct _cpuid4_info_regs * base) __cache_cpumap_setup() argument
1001 init_cache_level(unsigned int cpu) init_cache_level() argument
1019 get_cache_id(int cpu,struct _cpuid4_info_regs * id4_regs) get_cache_id() argument
1030 populate_cache_leaves(unsigned int cpu) populate_cache_leaves() argument
1177 cache_ap_online(unsigned int cpu) cache_ap_online() argument
1203 cache_ap_offline(unsigned int cpu) cache_ap_offline() argument
[all...]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi6220.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
[all …]
/openbmc/qemu/target/avr/
H A Dcpu.h2 * QEMU AVR CPU
4 * Copyright (c) 2016-2020 Michael Rolnik
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
24 #include "cpu-qom.h"
25 #include "exec/cpu-defs.h"
28 #error "AVR 8-bit does not support user mode"
45 /* Number of CPU registers */
61 /* CPU registers, IO registers, and SRAM */
63 /* CPU registers specifically, these are mapped at the start of data */
67 * mapped peripherals, mapped just after CPU registers
[all …]
/openbmc/linux/arch/arc/include/asm/
H A Dmmu_context.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -Refactored get_new_mmu_context( ) to only handle live-mm.
7 * retiring-mm handled in other hooks
10 * -Major rewrite of Core ASID allocation routine get_new_mmu_context
21 #include <asm-generic/mm_hooks.h>
25 * MMU tags TLBs with an 8-bit ASID, avoiding need to flush the TLB on
26 * context-switch.
28 * ASID is managed per cpu, so task threads across CPUs can have different
32 * Each task is assigned unique ASID, with a simple round-robin allocator
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
12 #include <asm/arch-tegra/clk_rst.h>
13 #include <asm/arch-tegra/pmc.h>
14 #include <asm/arch-tegra/scu.h>
15 #include "cpu.h"
24 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; in get_num_cpus()
48 * ------------------------------
50 * PLLX_BASE n 17: 8 10
52 * PLLX_MISC cpcon 11: 8 4
[all …]

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