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/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
28 mode "640x480-60"
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
[all …]
H A Dmatroxfb.rst294 maxclk:X maximum dotclock. X can be specified in MHz, kHz or Hz. Default is
299 70 for modes derived from `vesa` with yres <= 400, 60Hz for
327 - 83 MHz on G200
328 - 66 MHz on Millennium I
329 - 60 MHz on Millennium II
335 - my Millennium G200 oscillator has frequency range from 35 MHz to 380 MHz
336 (and it works with 8bpp on about 320 MHz dotclocks (and changed mclk)).
337 But Matrox says on product sheet that VCO limit is 50-250 MHz, so I believe
364 It is time to redraw whole screen 1000 times in 1024x768, 60Hz. It is
369 faster, it is kernel-space only time on P-II/350 MHz, Millennium I in 33 MHz
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
/openbmc/linux/drivers/video/fbdev/
H A Dmacmodes.c36 /* 512x384, 60Hz, Non-Interlaced (15.67 MHz dot clock) */
37 "mac2", 60, 512, 384, 63828, 80, 16, 19, 1, 32, 3,
40 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
41 "mac5", 60, 640, 480, 39722, 32, 32, 33, 10, 96, 2,
44 /* 640x480, 67Hz, Non-Interlaced (30.0 MHz dotclock) */
48 /* 640x870, 75Hz (portrait), Non-Interlaced (57.28 MHz dot clock) */
52 /* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
56 /* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
57 "mac10", 60, 800, 600, 25000, 72, 56, 23, 1, 128, 4,
60 /* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
[all …]
H A Dvalkyriefb.h79 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
126 /* Register values for 1024x768, 60Hz mode (14) */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
151 /* Register values for 800x600, 60Hz mode (10) */
154 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
[all …]
/openbmc/openbmc/meta-nuvoton/recipes-nuvoton/program-edid/program-edid/
H A Dedid.json63 "Pixel clock (MHz)": 154.0,
98 "Pixel clock (MHz)": 25.17,
116 "Pixel clock (MHz)": 170,
130 "1024x768 @ 60 Hz": true,
136 "640x480 @ 60 Hz": true,
143 "800x600 @ 60 Hz": true,
175 "Frequency": 60,
185 "Frequency": 60,
190 "Frequency": 60,
/openbmc/linux/arch/powerpc/boot/
H A Dutil.S22 * timebase in nanoseconds. This used to be hardcoded to be 60ns
23 * (period of 66MHz/4). Now a variable is used that is initialized to
24 * 60 for backward compatibility, but it can be overridden as necessary
32 .long 60
43 * timebase_period_ns defaults to 60 (16.6MHz) */
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dphy_shim.h45 #define FRA_ERR_20MHZ 60
80 /* Index for first 20MHz OFDM SISO rate */
82 /* Index for first 20MHz OFDM CDD rate */
84 /* Index for first 40MHz OFDM SISO rate */
86 /* Index for first 40MHz OFDM CDD rate */
87 #define WL_TX_POWER_OFDM40_CDD_FIRST 60
89 /* Index for first 20MHz MCS SISO rate */
91 /* Index for first 20MHz MCS CDD rate */
93 /* Index for first 20MHz MCS STBC rate */
95 /* Index for first 20MHz MCS SDM rate */
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_dfs.c29 /* 20MHz */
34 RADAR_SPEC(3, 60, 20, 46, 300, 640, 80, 4900, 10100, 80, 0,
38 /* 40MHz */
43 RADAR_SPEC(3, 60, 20, 46, 300, 640, 80, 4900, 10100, 80, 0,
47 /* 80MHz */
52 RADAR_SPEC(3, 60, 20, 46, 300, 640, 80, 4900, 10100, 80, 0,
59 /* 20MHz */
66 RADAR_SPEC(2, 60, 15, 63, 640, 2080, 32, 19600, 40200, 32, 0,
68 /* 40MHz */
75 RADAR_SPEC(2, 60, 15, 63, 640, 2080, 32, 19600, 40200, 32, 0,
[all …]
/openbmc/u-boot/include/configs/
H A Domap3_cairo.h92 "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
93 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
94 "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
95 "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
96 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
97 "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
98 "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
99 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
100 "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
101 "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
[all …]
H A Dtao3530.h44 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
82 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
85 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
145 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-enumstd.rst136 ``V4L2_STD_PAL_60`` is a hybrid standard with 525 lines, 60 Hz refresh
137 rate, and PAL color modulation with a 4.43 MHz color subcarrier. Some
139 a 50/60 Hz agnostic PAL TV.
147 ``V4L2_STD_NTSC_443`` is a hybrid standard with 525 lines, 60 Hz refresh
148 rate, and NTSC color modulation with a 4.43 MHz color subcarrier.
268 * - Nominal radio-frequency channel bandwidth (MHz)
280 * - Sound carrier relative to vision carrier (MHz)
331 New Zealand uses a sound carrier displaced 5.4996 ± 0.0005 MHz from
337 is being introduced. The second carrier is 5.85 MHz above the vision
343 second sound carrier is 6.552 MHz above the vision carrier and is
[all …]
/openbmc/u-boot/doc/
H A DREADME.m54418twr119 make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock
120 make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock
121 make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
122 …make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input c…
123 make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock
124 make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock
135 CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
136 INP CLK 50 MHz VCO CLK 500 MHz
152 ethaddr=00:e0:0c:bc:e5:60
182 cpufreq = 250 MHz
[all …]
/openbmc/u-boot/board/armadeus/apf27/
H A Dapf27.h27 * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
29 #define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */
33 #define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
36 #define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */
38 #define CONFIG_SPLL_FREQ 300 /* MHz */
41 #define CONFIG_ARM_FREQ 399 /* up to 400 MHz */
46 #define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */
47 #define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */
48 #define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */
49 #define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */
[all …]
/openbmc/u-boot/board/samsung/smdkc100/
H A Donenand.c54 * 166 MHz, 134 Mhz : 3 in onenand_board_init()
55 * 100 Mhz, 60 Mhz : 2 in onenand_board_init()
/openbmc/u-boot/board/ge/bx50v3/
H A Dbx50v3.c304 /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ in mx6_rgmii_rework()
311 /* set to 125 MHz from local PLL source */ in mx6_rgmii_rework()
376 .refresh = 60,
396 .refresh = 60,
404 .hsync_len = 60,
418 /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2) in enable_videopll()
426 * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz in enable_videopll()
459 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */ in setup_display_b850v3()
507 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */ in setup_display_bx50v3()
776 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60"); in board_late_init()
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
16 {cpu_to_le16(160), {50, 58, 60, 62, 64, 52, 54, 56},
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dmaxim,max8952.yaml62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
91 pmic@60 {
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-of-arasan.c81 #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
84 #define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
203 * met at 25MHz for Default Speed mode, those controllers work at
204 * 19MHz instead
401 * requirements met at 25MHz for Default Speed mode, in sdhci_arasan_set_clock()
402 * those controllers work at 19MHz instead. in sdhci_arasan_set_clock()
751 /* For 50MHz clock, 30 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
755 /* For 100MHz clock, 15 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
760 /* For 200MHz clock, 8 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
820 /* For 50MHz clock, 120 Taps are available */ in sdhci_zynqmp_sampleclk_set_phase()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmem.h110 /* Hynix part of Overo (165MHz optimized) 6.06ns */
136 /* Hynix part of AM/DM37xEVM (200MHz optimized) */
162 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
170 #define INFINEON_TRC_165 10 /* 60/6 = 10 */
188 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
196 #define MICRON_TRC_165 10 /* 60/6 = 10 */
225 /* Micron part (200MHz optimized) 5 ns */
251 /* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
294 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
302 #define NUMONYX_TRC_165 10 /* 60/6 = 10 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/
H A Dtypes.h21 #define SC_10MHZ 10000000U /* 10MHz */
22 #define SC_20MHZ 20000000U /* 20MHz */
23 #define SC_25MHZ 25000000U /* 25MHz */
24 #define SC_27MHZ 27000000U /* 27MHz */
25 #define SC_40MHZ 40000000U /* 40MHz */
26 #define SC_45MHZ 45000000U /* 45MHz */
27 #define SC_50MHZ 50000000U /* 50MHz */
28 #define SC_60MHZ 60000000U /* 60MHz */
29 #define SC_66MHZ 66666666U /* 66MHz */
30 #define SC_74MHZ 74250000U /* 74.25MHz */
[all …]
/openbmc/linux/drivers/media/test-drivers/vivid/
H A Dvivid-vbi-gen.c25 const unsigned rate = 5000000; /* WSS has a 5 MHz transmission rate */ in vivid_vbi_gen_wss_raw()
51 const unsigned rate = 6937500 / 10; /* Teletext has a 6.9375 MHz transmission rate */ in vivid_vbi_gen_teletext_raw()
86 const unsigned rate = 1000000; /* CC has a 1 MHz transmission rate */ in vivid_vbi_gen_cc_raw()
188 sys_tz.tz_minuteswest > tm.tm_min + tm.tm_hour * 60) in vivid_vbi_gen_set_time_of_day()
200 packet[12] = calc_parity(0x40 | ((sys_tz.tz_minuteswest / 60) & 0x1f)); in vivid_vbi_gen_set_time_of_day()
202 packet[12] = calc_parity(0x40 | ((24 + sys_tz.tz_minuteswest / 60) & 0x1f)); in vivid_vbi_gen_set_time_of_day()
250 unsigned frame = seqnr % 60; in vivid_vbi_gen_sliced()
296 frame = seqnr % (30 * 60); in vivid_vbi_gen_sliced()
/openbmc/u-boot/board/beckhoff/mx53cx9020/
H A Dmx53cx9020_video.c21 .refresh = 60,
24 .pixclock = 39721, /* picosecond (25.175 MHz) */
26 .right_margin = 60,
/openbmc/u-boot/board/menlo/m53menlo/
H A Dm53menlo.c200 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to in enable_lvds_clock()
201 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 . in enable_lvds_clock()
222 * Set LVDS clock to 9 MHz for the display. The PLL4 is set to in enable_lvds_etm0430g0dh6()
223 * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 . in enable_lvds_etm0430g0dh6()
231 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to in enable_lvds_etm0700g0dh6()
232 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 . in enable_lvds_etm0700g0dh6()
295 .refresh = 60,
298 .pixclock = 111111, /* picosecond (9 MHz) */
316 .refresh = 60,
319 .pixclock = 30048, /* picosecond (33.28 MHz) */
[all …]
/openbmc/linux/tools/edid/
H A Dedid.S149 Bit 5 640x480 @ 60 Hz
154 Bit 0 800x600 @ 60 Hz */
161 Bit 3 1024x768 @ 60 Hz
176 Bits 5-0 Vertical frequency, less 60 (60-123 Hz) */
177 std_vres: .byte (XY_RATIO<<6)+VFREQ-60
181 /* Pixel clock in 10 kHz units. (0.-655.35 MHz, little-endian) */
262 to 10 MHz multiple (10-2550 MHz) */

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