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/openbmc/linux/drivers/gpu/drm/ci/xfails/
H A Dmsm-sdm845-fails.txt10 kms_color@pipe-A-ctm-0-5,Fail
24 kms_cursor_legacy@cursor-vs-flip-atomic,Fail
25 kms_cursor_legacy@cursor-vs-flip-atomic-transitions,Fail
26 kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size,Fail
27 kms_cursor_legacy@cursor-vs-flip-legacy,Fail
28 kms_cursor_legacy@cursor-vs-flip-toggle,Fail
29 kms_cursor_legacy@cursor-vs-flip-varying-size,Fail
30 kms_cursor_legacy@cursorA-vs-flipA-toggle,Fail
31 kms_cursor_legacy@flip-vs-cursor-atomic,Fail
32 kms_cursor_legacy@flip-vs-cursor-crc-atomic,Fail
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dlmmi_helper.c58 LMIValue vs, vt; in helper_paddsb() local
61 vs.d = fs; in helper_paddsb()
64 int r = vs.sb[i] + vt.sb[i]; in helper_paddsb()
65 vs.sb[i] = SATSB(r); in helper_paddsb()
67 return vs.d; in helper_paddsb()
72 LMIValue vs, vt; in helper_paddusb() local
75 vs.d = fs; in helper_paddusb()
78 int r = vs.ub[i] + vt.ub[i]; in helper_paddusb()
79 vs.ub[i] = SATUB(r); in helper_paddusb()
81 return vs.d; in helper_paddusb()
[all …]
/openbmc/linux/security/selinux/ss/
H A Dconstraint.h21 #define CEXPR_MAXDEPTH 5
28 #define CEXPR_NAMES 5 /* attr op names */
36 #define CEXPR_L1L2 32 /* low level 1 vs. low level 2 */
37 #define CEXPR_L1H2 64 /* low level 1 vs. high level 2 */
38 #define CEXPR_H1L2 128 /* high level 1 vs. low level 2 */
39 #define CEXPR_H1H2 256 /* high level 1 vs. high level 2 */
40 #define CEXPR_L1H1 512 /* low level 1 vs. high level 1 */
41 #define CEXPR_L2H2 1024 /* low level 2 vs. high level 2 */
48 #define CEXPR_INCOMP 5 /* incomp */
/openbmc/qemu/tests/tcg/s390x/
H A Dvxeh2_vlstr.c88 S390Vector vs = { .d[0] = 0x8FEEDDCCBBAA9988ull, in main() local
93 .h[4] = 0x9988, .h[5] = 0xBBAA, .h[6] = 0xDDCC, .h[7] = 0x8FEE }; in main()
97 .h[4] = 0x6677, .h[5] = 0x4455, .h[6] = 0x2233, .h[7] = 0x0711 }; in main()
102 vler(&vd, &vs, ES16); in main()
105 vster(&vs, &vd, ES16); in main()
108 vlbr(&vd, &vs, ES16); in main()
111 vstbr(&vs, &vd, ES16); in main()
114 vlebrh(&vd, &ss64, 5); in main()
115 if (0xEDFE != vd.h[5]) { in main()
119 vstebrh(&vs, (uint8_t *)&sd64 + 4, 7); in main()
H A Dvxeh2_vs.c68 S390Vector vs = { .d[0] = 0x8FEEDDCCBBAA9988ull, in main() local
74 vsi.b[ix] = (1 + (5 ^ ~ix)) & 7; in main()
77 vsl(&vd, &vs, &vsi); in main()
80 vsra(&vd, &vs, &vsi); in main()
83 vsrl(&vd, &vs, &vsi); in main()
86 vsld(&vd, &vs, &vsi, 3); in main()
89 vsrd(&vd, &vs, &vsi, 15); in main()
/openbmc/qemu/ui/
H A Dvnc-enc-tight.c62 { 512, 32, 6, 65536, 0, 0, 0, 0, 0, 0, 4, 5, 10000, 23000 },
65 { 10240, 1024, 12, 65536, 5, 5, 3, 0, 0, 0, 32, 25, 5000, 12000 },
67 { 32768, 2048, 12, 4096, 7, 7, 5, 4, 150, 380, 32, 50, 3000, 8000 },
69 { 65536, 2048, 16, 4096, 8, 8, 7, 5, 180, 450, 64, 70, 1000, 2500 },
75 static int tight_send_framebuffer_update(VncState *vs, int x, int y,
107 { 5, PNG_ALL_FILTERS },
114 static int send_png_rect(VncState *vs, int x, int y, int w, int h,
117 static bool tight_can_send_png_rect(VncState *vs, int w, int h) in tight_can_send_png_rect() argument
119 if (vs->tight->type != VNC_ENCODING_TIGHT_PNG) { in tight_can_send_png_rect()
123 if (surface_bytes_per_pixel(vs->vd->ds) == 1 || in tight_can_send_png_rect()
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H A Dvnc.c71 static int vnc_cursor_define(VncState *vs);
72 static void vnc_update_throttle_offset(VncState *vs);
74 static void vnc_set_share_mode(VncState *vs, VncShareMode mode) in vnc_set_share_mode() argument
85 vs->ioc, mn[vs->share_mode], mn[mode]); in vnc_set_share_mode()
88 switch (vs->share_mode) { in vnc_set_share_mode()
90 vs->vd->num_connecting--; in vnc_set_share_mode()
93 vs->vd->num_shared--; in vnc_set_share_mode()
96 vs->vd->num_exclusive--; in vnc_set_share_mode()
102 vs->share_mode = mode; in vnc_set_share_mode()
104 switch (vs->share_mode) { in vnc_set_share_mode()
[all …]
H A Dvnc.h68 typedef int VncReadEvent(VncState *vs, uint8_t *data, size_t len);
70 typedef void VncWritePixels(VncState *vs, void *data, int size);
72 typedef void VncSendHextileTile(VncState *vs,
250 VncState *vs; member
368 VNC_AUTH_RA2 = 5,
475 #define VNC_MSG_CLIENT_POINTER_EVENT 5
552 size_t vnc_client_read_buf(VncState *vs, uint8_t *data, size_t datalen);
553 size_t vnc_client_write_buf(VncState *vs, const uint8_t *data, size_t datalen);
556 void vnc_write(VncState *vs, const void *data, size_t len);
557 void vnc_write_u32(VncState *vs, uint32_t value);
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_fixed_vs_pe_retimer.c28 * embedded retimer chip. This retimer chip is referred as fixed vs pe retimer.
89 /* Force LTTPR to output desired VS and PE */ in dp_fixed_vs_pe_set_retimer_lane_settings()
113 /* Fixed VS/PE specific: Force CR AUX RD Interval to at least 16ms */ in perform_fixed_vs_pe_nontransparent_training_sequence()
117 /* Fixed VS/PE specific: Toggle link rate */ in perform_fixed_vs_pe_nontransparent_training_sequence()
131 /* Fixed VS/PE specific: Toggle link rate back*/ in perform_fixed_vs_pe_nontransparent_training_sequence()
343 /* EPR #361076 - write as a 5-byte burst, in dp_perform_fixed_vs_pe_training_sequence_legacy()
375 /* Vendor specific: Update VS and PE to DPRX requested value */ in dp_perform_fixed_vs_pe_training_sequence_legacy()
405 /* 5. check CR done*/ in dp_perform_fixed_vs_pe_training_sequence_legacy()
411 /* 6. max VS reached*/ in dp_perform_fixed_vs_pe_training_sequence_legacy()
425 /* 8. update VS/PE/PC2 in lt_settings*/ in dp_perform_fixed_vs_pe_training_sequence_legacy()
[all …]
/openbmc/linux/net/rose/
H A Drose_out.c37 skb->data[2] |= (rose->vr << 5) & 0xE0; in rose_send_iframe()
38 skb->data[2] |= (rose->vs << 1) & 0x0E; in rose_send_iframe()
60 start = (skb_peek(&rose->ack_queue) == NULL) ? rose->va : rose->vs; in rose_kick()
66 rose->vs = start; in rose_kick()
88 rose->vs = (rose->vs + 1) % ROSE_MODULUS; in rose_kick()
95 } while (rose->vs != end && in rose_kick()
/openbmc/linux/drivers/hwmon/pmbus/
H A Dibm-cffps.c44 #define CFFPS_MFR_OC_FAULT BIT(5)
159 rc = snprintf(data, 5, "%04X", rc); in ibm_cffps_debugfs_read()
180 snprintf(&data[i * 4], 5, "%04X", rc); in ibm_cffps_debugfs_read()
485 enum versions vs = cffps_unknown; in ibm_cffps_probe() local
492 vs = (uintptr_t)md; in ibm_cffps_probe()
496 vs = (enum versions)id->driver_data; in ibm_cffps_probe()
499 if (vs == cffps_unknown) { in ibm_cffps_probe()
521 vs = cffps1; in ibm_cffps_probe()
523 vs = cffps2; in ibm_cffps_probe()
526 vs = cffps2; in ibm_cffps_probe()
[all …]
/openbmc/u-boot/board/freescale/mpc8548cds/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
43 * 5 = 5/4 clock delay in fsl_ddr_board_options()
/openbmc/u-boot/board/socrates/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
43 * 5 = 5/4 clock delay in fsl_ddr_board_options()
/openbmc/u-boot/board/freescale/mpc8555cds/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
43 * 5 = 5/4 clock delay in fsl_ddr_board_options()
/openbmc/u-boot/board/freescale/mpc8541cds/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
43 * 5 = 5/4 clock delay in fsl_ddr_board_options()
/openbmc/u-boot/board/freescale/mpc8568mds/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
43 * 5 = 5/4 clock delay in fsl_ddr_board_options()
/openbmc/u-boot/board/sbc8641d/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
43 * 5 = 5/4 clock delay in fsl_ddr_board_options()
/openbmc/linux/net/lapb/
H A Dlapb_out.c48 frame[0] |= lapb->vs << 1; in lapb_send_iframe()
56 *frame |= lapb->vr << 5; in lapb_send_iframe()
57 *frame |= lapb->vs << 1; in lapb_send_iframe()
61 lapb->dev, lapb->state, poll_bit, lapb->vs, lapb->vr); in lapb_send_iframe()
72 start = !skb_peek(&lapb->ack_queue) ? lapb->va : lapb->vs; in lapb_kick()
77 lapb->vs = start; in lapb_kick()
99 lapb->vs = (lapb->vs + 1) % modulus; in lapb_kick()
106 } while (lapb->vs != end && (skb = skb_dequeue(&lapb->write_queue)) != NULL); in lapb_kick()
191 if (lapb->vs == nr) { in lapb_check_iframes_acked()
H A Dlapb_subr.c83 * Validate that the value of nr is between va and vs. Return true or
93 while (vc != lapb->vs) { in lapb_validate_nr()
99 return nr == lapb->vs; in lapb_validate_nr()
190 frame->nr = (skb->data[0] >> 5) & 0x07; in lapb_decode()
197 frame->nr = (skb->data[0] >> 5) & 0x07; in lapb_decode()
248 *dptr |= (lapb->vr << 5); in lapb_send_control()
273 *dptr++ = (lapb->vs << 1) & 0xFE; in lapb_transmit_frmr()
280 lapb_dbg(1, "(%p) S%d TX FRMR %5ph\n", in lapb_transmit_frmr()
287 *dptr = (lapb->vs << 1) & 0x0E; in lapb_transmit_frmr()
288 *dptr |= (lapb->vr << 5) & 0xE0; in lapb_transmit_frmr()
/openbmc/u-boot/board/freescale/mpc8544ds/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
43 * 5 = 5/4 clock delay in fsl_ddr_board_options()
/openbmc/u-boot/board/freescale/mpc8610hpcd/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
43 * 5 = 5/4 clock delay in fsl_ddr_board_options()
/openbmc/u-boot/board/freescale/mpc8536ds/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
43 * 5 = 5/4 clock delay in fsl_ddr_board_options()
/openbmc/u-boot/board/freescale/mpc8569mds/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
43 * 5 = 5/4 clock delay in fsl_ddr_board_options()
/openbmc/u-boot/board/xes/xpedite520x/
H A Dddr.c34 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
46 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
58 * 5 = 5/4 clock delay in fsl_ddr_board_options()
/openbmc/linux/drivers/media/i2c/
H A Dtda1997x_regs.h130 #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */
131 #define DETECT_5V_B BIT(1) /* 5V present on input B */
132 #define DETECT_5V_A BIT(0) /* 5V present on input A */
158 #define HPD_MAN_CTRL_5VEN BIT(2) /* Output 5V */
169 #define VDP_CTRL_COMPDEL_BP BIT(5) /* bypass compdel */
190 #define VHREF_HSYNC_SEL_HS BIT(0) /* 1=HS 0=VS */
193 #define AUDIO_OUT_ENABLE_ACLK BIT(5)
240 #define HDMI_FLAGS_EESS BIT(5) /* EESS detected */
302 #define HDCP_DE_REGEN_EN BIT(5) /* enable regen mode */
307 #define HDCP_DE_COMP_OR 5L
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