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/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main_regs.h21 TARGET_ANA_AC_POL = 4,
62 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4)
65 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ argument
66 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
67 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ argument
68 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)
71 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
72 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
73 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
74 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
[all …]
/openbmc/linux/drivers/phy/microchip/
H A Dsparx5_serdes_regs.h32 #define SD10G_LANE_LANE_01(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 4, 0, 1, 4)
35 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ argument
36 FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
37 #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\ argument
38 FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
40 #define SD10G_LANE_LANE_01_CFG_RXDET_EN BIT(4)
41 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\ argument
42 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
43 #define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\ argument
44 FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h35 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4)
38 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ argument
39 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
40 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ argument
41 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
44 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4)
47 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ argument
48 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
49 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ argument
50 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
[all …]
/openbmc/linux/include/soc/mscc/
H A Docelot_dev.h14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
17 #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0)) argument
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
27 #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15)) argument
29 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15) argument
30 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8)) argument
32 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8) argument
33 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1)) argument
35 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1) argument
38 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4)) argument
[all …]
H A Docelot_hsio.h90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23)) argument
92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23) argument
93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18)) argument
95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18) argument
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16)) argument
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16) argument
103 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6)) argument
105 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6) argument
106 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0)) argument
114 #define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6)) argument
[all …]
H A Docelot_qsys.h17 #define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4)
25 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8)) argument
27 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8) argument
28 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0)) argument
33 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8)) argument
35 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8) argument
36 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0)) argument
41 #define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5)) argument
43 #define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5) argument
44 #define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2)) argument
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D014.out8 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
10 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
14 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
16 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
18 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
22 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
24 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
26 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D171.out8 3.500 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 3.500 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
16 read 4/4 bytes at offset 510
17 4 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
21 1 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
37 1 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
53 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
57 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
59 read 4/4 bytes at offset 510
60 4 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D013.out8 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
10 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
14 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
16 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
18 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
22 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
24 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
26 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D022.out8 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
10 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
14 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
16 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
18 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
20 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
22 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
24 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
26 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D058.out6 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
8 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
10 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
12 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
17 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
19 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
23 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
25 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
29 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
31 4 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h9 #define ICPU_GPR(x) (0x4 * (x)) argument
30 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4)) argument
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4)
32 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4) argument
41 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) argument
43 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) argument
44 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
45 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
54 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) argument
56 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) argument
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h9 #define ICPU_GPR(x) (0x4 * (x)) argument
30 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4)) argument
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4)
32 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4) argument
42 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) argument
44 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) argument
45 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
46 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
55 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) argument
57 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) argument
[all …]
/openbmc/qemu/pc-bios/
HDopenbios-sparc32 ... H P 4 p x x ` 0 H P p x 0 H 4 P p H p P , \ P ...
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h9 #define ICPU_GPR(x) (0x4 * (x)) argument
23 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(4)
35 #define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
36 #define ICPU_PI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
41 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) argument
43 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) argument
44 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
45 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
54 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) argument
56 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) argument
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h9 #define ICPU_GPR(x) (0x4 * (x)) argument
29 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 6) & GENMASK(7, 6)) argument
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(7, 6)) >> 4) argument
32 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER(x) (((x) << 4) & GENMASK(5, 4)) argument
33 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER_M GENMASK(5, 4)
34 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4) argument
44 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) argument
46 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) argument
47 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
48 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h9 #define ICPU_GPR(x) (0x4 * (x)) argument
28 #define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(4)
37 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) argument
39 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) argument
40 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
41 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
50 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) argument
52 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) argument
53 #define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1)) argument
54 #define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
[all …]
/openbmc/linux/arch/mips/crypto/
H A Dchacha-core.S31 #define X(n) X ## n macro
48 * They are used to handling the last bytes which are not multiple of 4.
71 #define FOR_EACH_WORD(x) \ argument
72 x( 0); \
73 x( 1); \
74 x( 2); \
75 x( 3); \
76 x( 4); \
77 x( 5); \
78 x( 6); \
[all …]
/openbmc/linux/arch/mips/include/asm/sibyte/
H A Dsb1250_scd.h29 * System Revision Register (Table 4-1)
36 #define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION) argument
37 #define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION) argument
84 #define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE)
85 #define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE) argument
86 #define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE) argument
100 #define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS)
101 #define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS) argument
102 #define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS) argument
108 #define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART) argument
[all …]
H A Dsb1250_mc.h34 #define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL) argument
35 #define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL) argument
38 #define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP)
39 #define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP) argument
40 #define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP) argument
46 #define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP)
47 #define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP) argument
48 #define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP) argument
54 #define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP)
55 #define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP) argument
[all …]
/openbmc/linux/include/math-emu/
H A Dquad.h33 #define _FP_FRACTBITS_Q (4*_FP_W_TYPE_SIZE)
79 #define FP_DECL_Q(X) _FP_DECL(4,X) argument
80 #define FP_UNPACK_RAW_Q(X,val) _FP_UNPACK_RAW_4(Q,X,val) argument
81 #define FP_UNPACK_RAW_QP(X,val) _FP_UNPACK_RAW_4_P(Q,X,val) argument
82 #define FP_PACK_RAW_Q(val,X) _FP_PACK_RAW_4(Q,val,X) argument
83 #define FP_PACK_RAW_QP(val,X) \ argument
86 _FP_PACK_RAW_4_P(Q,val,X); \
89 #define FP_UNPACK_Q(X,val) \ argument
91 _FP_UNPACK_RAW_4(Q,X,val); \
92 _FP_UNPACK_CANONICAL(Q,4,X); \
[all …]
/openbmc/linux/drivers/net/phy/mscc/
H A Dmscc_ptp.h16 #define BIU_BLK_ID(x) ((x) << 11) argument
17 #define BIU_CSR_ADDR(x) (x) argument
36 #define ANA_ETH1_NTX_PROT_SIG_OFF(x) (((x) << 16) & ANA_ETH1_NTX_PROT_SIG_OFF_MASK) argument
54 #define ANA_ETH1_NTX_PROT_VLAN_TPID(x) (((x) << 16) & ANA_ETH1_NTX_PROT_VLAN_TPID_MASK) argument
59 #define PTP_ANA_EGR_ENCAP_FLOW_MODE(x) (((x) << 20) & PTP_ANA_EGR_ENCAP_FLOW_MODE_MASK) argument
61 #define PTP_ANA_INGR_ENCAP_FLOW_MODE(x) (((x) << 16) & PTP_ANA_INGR_ENCAP_FLOW_MODE_MASK) argument
62 #define PTP_ANALYZER_MODE_EGR_ENA_MASK GENMASK(6, 4)
63 #define PTP_ANALYZER_MODE_EGR_ENA(x) (((x) << 4) & PTP_ANALYZER_MODE_EGR_ENA_MASK) argument
65 #define PTP_ANALYZER_MODE_INGR_ENA(x) ((x) & PTP_ANALYZER_MODE_INGR_ENA_MASK) argument
77 #define ANA_ETH1_NXT_PROT_ETYPE_MATCH(x) ((x) & ANA_ETH1_NXT_PROT_ETYPE_MATCH_MASK) argument
[all …]
/openbmc/linux/lib/crypto/
H A Dchacha.c16 static void chacha_permute(u32 *x, int nrounds) in chacha_permute() argument
24 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
25 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 16); in chacha_permute()
26 x[2] += x[6]; x[14] = rol32(x[14] ^ x[2], 16); in chacha_permute()
27 x[3] += x[7]; x[15] = rol32(x[15] ^ x[3], 16); in chacha_permute()
29 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute()
30 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute()
31 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute()
32 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute()
34 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute()
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dni_reg.h30 # define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0) argument
35 # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4) argument
38 # define NI_GRPH_PRESCALE_BYPASS (1 << 4)
41 # define NI_OVL_PRESCALE_BYPASS (1 << 4)
44 # define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0) argument
48 # define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4) argument
51 # define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0) argument
56 # define NI_OUTPUT_CSC_PROG_COEFF 4
58 # define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4) argument
61 # define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0) argument
[all …]
H A Dcik_reg.h36 # define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0) argument
40 # define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) argument
45 # define CIK_GRPH_Z(x) (((x) & 0x3) << 4) argument
46 # define CIK_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) argument
51 # define CIK_GRPH_FORMAT(x) (((x) & 0x7) << 8) argument
59 # define CIK_GRPH_FORMAT_MONO16 4
66 # define CIK_GRPH_FORMAT_BGRA1010102 4
70 # define CIK_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) argument
75 # define CIK_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) argument
80 # define CIK_ADDR_SURF_TILE_SPLIT_1KB 4
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