| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | hw_data.c | 32 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
33 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
34 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
35 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
36 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
37 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
38 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
43 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
44 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
45 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
[all …]
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| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | hw_data.c | 36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
[all …]
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| /openbmc/linux/arch/x86/kernel/ |
| H A D | tsc_msr.c | 19 #define MAX_NUM_FREQS 16 /* 4 bits to select the frequency */
22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
34 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
[all …]
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| /openbmc/linux/drivers/scsi/qla2xxx/ |
| H A D | qla_devtbl.h | 8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
18 "QLA2342", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10a */
20 "QLA2350", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x10c */
21 "QLA2352", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10d */
22 "QLA2352", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10e */
29 "QLA2360", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x115 */
[all …]
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| /openbmc/linux/drivers/clk/uniphier/ |
| H A D | clk-uniphier-sys.c | 24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
40 UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1)
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
[all …]
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| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | cpu.c | 35 return 4; in get_num_cpus()
51 * PLLX_BASE m 4: 0 5
52 * PLLX_MISC cpcon 11: 8 4
55 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
56 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
57 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
58 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
59 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
69 * PLLX_BASE m 4: 0 5
[all …]
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| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-exynos3250.c | 97 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
253 SRC_LEFTBUS, 4, 1),
258 SRC_RIGHTBUS, 4, 1),
270 MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
283 MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
284 MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
288 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
293 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
297 MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
298 MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
[all …]
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| /openbmc/u-boot/arch/arm/mach-imx/mx7ulp/ |
| H A D | clock.c | 69 if (index < 4 || index > 7) in get_lpuart_clk()
72 return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]); in get_lpuart_clk()
86 if (i2c_num < 4 || i2c_num > 7) in enable_i2c_clk()
90 pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false); in enable_i2c_clk()
91 pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK); in enable_i2c_clk()
92 pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true); in enable_i2c_clk()
94 pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false); in enable_i2c_clk()
108 if (i2c_num < 4 || i2c_num > 7) in imx_get_i2cclk()
111 return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]); in imx_get_i2cclk()
151 /* 158MHz / 1 = 158MHz */ in init_clk_usdhc()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu11_driver_if_vangogh.h | 45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
60 #define NUM_WM_RANGES 4
110 #define NUM_FCLK_DPM_LEVELS 4
124 //Freq in MHz
159 #define THROTTLER_STATUS_BIT_THM_CORE 4
168 uint16_t GfxclkFrequency; //[MHz]
169 uint16_t SocclkFrequency; //[MHz]
170 uint16_t VclkFrequency; //[MHz]
[all …]
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| H A D | smu13_driver_if_yellow_carp.h | 29 #define SMU13_YELLOW_CARP_DRIVER_IF_VERSION 4
45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
60 #define NUM_WM_RANGES 4
109 #define NUM_DF_PSTATE_LEVELS 4
119 //Freq in MHz
148 #define THROTTLER_STATUS_BIT_THM_CORE 4
159 uint16_t GfxclkFrequency; //[MHz]
160 uint16_t SocclkFrequency; //[MHz]
[all …]
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | opp2xxx.h | 69 #define R1_CLKSEL_L3 (4 << 0)
71 #define R1_CLKSEL_USB (4 << 25)
82 #define R1_CLKSEL_MDM (4 << 0)
123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
[all …]
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| /openbmc/u-boot/board/boundary/nitrogen6x/ |
| H A D | ddr-setup.cfg | 11 * Addr-type register length (1,2 or 4 bytes)
18 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
20 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
22 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
25 DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
26 DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
27 DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
28 DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
29 DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
30 DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
[all …]
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| /openbmc/u-boot/board/toradex/apalis_imx6/ |
| H A D | ddr-setup.cfg | 12 * Addr-type register length (1,2 or 4 bytes)
19 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
21 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
23 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
26 DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
27 DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
28 DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
29 DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
30 DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
31 DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
[all …]
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| /openbmc/u-boot/board/toradex/colibri_imx6/ |
| H A D | ddr-setup.cfg | 12 * Addr-type register length (1,2 or 4 bytes)
19 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
21 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
23 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
26 DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
27 DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
28 DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
29 DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
30 DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
31 DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
[all …]
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| /openbmc/u-boot/arch/arm/mach-omap2/omap3/ |
| H A D | lowlevel_init.S | 33 mcr p15, 0, r0, c7, c10, 4 @ DSB
199 /* DPLL(1-4) PARAM TABLES */
208 /* 12MHz */
216 /* 13MHz */
224 /* 19.2MHz */
232 /* 26MHz */
240 /* 38.4MHz */
255 /* 12MHz */
263 /* 13MHz */
271 /* 19.2MHz */
[all …]
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| /openbmc/linux/drivers/clk/spear/ |
| H A D | spear1340_clock.c | 58 #define SPEAR1340_UART0_CLK_SHIFT 4
81 #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4
125 #define SPEAR1340_FSMC_CLK_ENB 4
136 #define SPEAR1340_GPT2_CLK_ENB 4
155 #define SPEAR1340_CEC1_CLK_ENB 4
164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
[all …]
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| /openbmc/u-boot/drivers/video/exynos/ |
| H A D | exynos_mipi_dsi_common.c | 17 #define MHZ (1000 * 1000) macro
18 #define FIN_HZ (24 * MHZ)
20 #define DFIN_PLL_MIN_HZ (6 * MHZ)
21 #define DFIN_PLL_MAX_HZ (12 * MHZ)
23 #define DFVCO_MIN_HZ (500 * MHZ)
24 #define DFVCO_MAX_HZ (1000 * MHZ)
42 DSIM_LANE_DATA3 = (1 << 4)
56 /* in case that data count is more then 4 */ in exynos_mipi_dsi_long_data_wr()
57 for (data_cnt = 0; data_cnt < data1; data_cnt += 4) { in exynos_mipi_dsi_long_data_wr()
59 * after sending 4bytes per one time, in exynos_mipi_dsi_long_data_wr()
[all …]
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| /openbmc/linux/drivers/media/i2c/cx25840/ |
| H A D | cx25840-audio.c | 17 * NTSC Color subcarrier freq * 8 = 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
26 * ref_freq = 28.636360 MHz
28 * ref_freq = 28.636363 MHz
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
47 * 432 MHz pre-postdivide in cx25840_set_audclk_freq()
53 * 196.6 MHz pre-postdivide in cx25840_set_audclk_freq()
54 * FIXME < 200 MHz is out of specified valid range in cx25840_set_audclk_freq()
68 /* src3/4/6_ctl */ in cx25840_set_audclk_freq()
69 /* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */ in cx25840_set_audclk_freq()
84 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
[all …]
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| /openbmc/linux/drivers/media/pci/cx18/ |
| H A D | cx18-av-audio.c | 25 * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz in set_audclk_freq()
41 * crystal value at all, it will assume 28.636360 MHz, the crystal in set_audclk_freq()
44 * xtal_freq = 28.636360 MHz in set_audclk_freq()
49 * Below I aim to run the PLLs' VCOs near 400 MHz to minimize error. in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
73 /* src3/4/6_ctl */ in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
82 /* AUD_COUNT = 0x2fff = 8 samples * 4 * 384 - 1 */ in set_audclk_freq()
88 * ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8 in set_audclk_freq()
[all …]
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| /openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/ |
| H A D | rs.h | 14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
31 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4),
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
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| /openbmc/u-boot/board/freescale/bsc9132qds/ |
| H A D | README | 23 ECC), up to 1333 MHz data rate
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
84 4. SPI flash
94 make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
95 make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
98 make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
[all …]
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| /openbmc/linux/Documentation/fb/ |
| H A D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
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| /openbmc/linux/drivers/clk/mvebu/ |
| H A D | dove.c | 26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/ |
| H A D | types.h | 21 #define SC_10MHZ 10000000U /* 10MHz */
22 #define SC_20MHZ 20000000U /* 20MHz */
23 #define SC_25MHZ 25000000U /* 25MHz */
24 #define SC_27MHZ 27000000U /* 27MHz */
25 #define SC_40MHZ 40000000U /* 40MHz */
26 #define SC_45MHZ 45000000U /* 45MHz */
27 #define SC_50MHZ 50000000U /* 50MHz */
28 #define SC_60MHZ 60000000U /* 60MHz */
29 #define SC_66MHZ 66666666U /* 66MHz */
30 #define SC_74MHZ 74250000U /* 74.25MHz */
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3328.h | 33 u32 reserved6[(0x100 - 0xb4) / 4];
35 u32 reserved7[(0x200 - 0x1d4) / 4];
40 u32 reserved9[(0x380 - 0x330) / 4];
47 #define MHz 1000000 macro
49 #define OSC_HZ (24 * MHz)
50 #define APLL_HZ (600 * MHz)
51 #define GPLL_HZ (576 * MHz)
52 #define CPLL_HZ (594 * MHz)
54 #define CLK_CORE_HZ (600 * MHz)
55 #define ACLKM_CORE_HZ (300 * MHz)
[all …]
|