/openbmc/linux/arch/arm/boot/dts/intel/pxa/ |
H A D | pxa2xx.dtsi | 58 pxairq: interrupt-controller@40d00000 { 67 gpio: gpio@40e00000 { 80 gcb0: gpio@40e00000 { 84 gcb1: gpio@40e00004 { 88 gcb2: gpio@40e00008 { 91 gcb3: gpio@40e0000c { 98 reg = <0x40100000 0x30>; 106 reg = <0x40200000 0x30>; 114 reg = <0x40700000 0x30>; 122 reg = <0x41600000 0x30>; [all …]
|
/openbmc/linux/Documentation/devicetree/bindings/timer/ |
H A D | marvell,armada-370-xp-timer.txt | 31 reg = <0x20300 0x30>, <0x21040 0x30>; 32 interrupts = <37>, <38>, <39>, <40>, <5>, <6>; 40 reg = <0x20300 0x30>, <0x21040 0x30>; 41 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
|
/openbmc/linux/drivers/pinctrl/mediatek/ |
H A D | pinctrl-mt7981.c | 87 PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1), 88 PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1), 89 PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1), 90 PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1), 91 PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), 92 PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1), 93 PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1), 94 PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1), 95 PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1), 96 PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1), [all …]
|
H A D | pinctrl-mt7986.c | 99 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1), 100 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1), 101 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1), 102 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1), 103 PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1), 104 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1), 105 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1), 106 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1), 112 PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1), 118 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1), [all …]
|
H A D | pinctrl-mt8173.c | 80 MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9), 133 MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9), 184 MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0), 185 MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0), 186 MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0), 187 MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0), 188 MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0), 189 MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1), 190 MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1), 191 MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1), [all …]
|
/openbmc/linux/drivers/gpu/drm/panel/ |
H A D | panel-newvision-nv3051d.c | 55 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); in panel_nv3051d_init_sequence() 99 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); in panel_nv3051d_init_sequence() 113 mipi_dsi_dcs_write_seq(dsi, 0xD7, 0x30); in panel_nv3051d_init_sequence() 138 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); in panel_nv3051d_init_sequence() 151 mipi_dsi_dcs_write_seq(dsi, 0x30, 0x2A); in panel_nv3051d_init_sequence() 214 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); in panel_nv3051d_init_sequence() 233 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); in panel_nv3051d_init_sequence() 443 .hsync_start = 640 + 40, 444 .hsync_end = 640 + 40 + 2, 445 .htotal = 640 + 40 + 2 + 80, [all …]
|
/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | dm814x-clocks.dtsi | 9 adpll_mpu_ck: adpll@40 { 24 reg = <0x80 0x30>; 35 reg = <0xb0 0x30>; 46 reg = <0xe0 0x30>; 57 reg = <0x110 0x30>; 68 reg = <0x140 0x30>; 79 reg = <0x170 0x30>; 90 reg = <0x1a0 0x30>; 101 reg = <0x1d0 0x30>; 112 reg = <0x200 0x30>; [all …]
|
/openbmc/linux/arch/sparc/crypto/ |
H A D | camellia_asm.S | 94 stx %o4, [%o1 + 0x30] ! k[12, 13] 105 stx %o4, [%o1 + 0xa0] ! k[40, 41] 136 std %f0, [%o1 + 0x30] ! k[12, 13] 152 stx %o4, [%o1 + 0xa0] ! k[40, 41] 171 ldx [%o1 + 0x30], %o4 ! k[12, 13] 174 stx %o4, [%o1 + 0x30] ! k[12, 13] 213 ldd [%o1 + 0x30], %f2 227 std %f0, [%o3 + 0x30] 262 ldd [%o0 + 0x30], %f16 275 ldd [%o0 + 0x30], %f16 [all …]
|
H A D | aes_asm.S | 61 ENCRYPT_TWO_ROUNDS_LAST(KEY_BASE + 40, I0, I1, T0, T1) 69 ENCRYPT_TWO_ROUNDS_LAST_2(KEY_BASE + 40, I0, I1, I2, I3, T0, T1, T2, T3) 78 ENCRYPT_TWO_ROUNDS(KEY_BASE + 40, I0, I1, T0, T1) \ 95 ENCRYPT_256_TWO_ROUNDS_2(KEY_BASE + 40, I0, I1, I2, I3, KEY_BASE + 0) \ 163 DECRYPT_TWO_ROUNDS_LAST(KEY_BASE + 40, I0, I1, T0, T1) 171 DECRYPT_TWO_ROUNDS_LAST_2(KEY_BASE + 40, I0, I1, I2, I3, T0, T1, T2, T3) 180 DECRYPT_TWO_ROUNDS(KEY_BASE + 40, I0, I1, T0, T1) \ 197 DECRYPT_256_TWO_ROUNDS_2(KEY_BASE + 40, I0, I1, I2, I3, KEY_BASE + 0) \ 257 AES_KEXPAND1(32, 38, 0x4, 40) 258 AES_KEXPAND2(34, 40, 42) [all …]
|
/openbmc/linux/drivers/net/wireless/marvell/mwifiex/ |
H A D | cfp.c | 35 0x30, 0x48, 0x60, 0x6c, 0 }; 43 0x24, 0x30, 0x48, 0x60, 0x6C, 0x90, 51 0x30, 0x48, 0x60, 0x6c, 0 }; 54 0x12, 0x16, 0x18, 0x24, 0x30, 0x48, 57 u16 region_code_index[MWIFIEX_MAX_REGION_CODE] = { 0x00, 0x10, 0x20, 0x30, 66 /* LGI 40M */ 70 /* SGI 40M */ 101 /* LG 40M */ 105 /* SG 40M */ 134 /* LG 40M */ [all …]
|
/openbmc/linux/drivers/media/dvb-frontends/ |
H A D | tda18271c2dd_maps.h | 153 { 164700000, 0x30 }, 180 { 194000000, 0x30 }, 222 { 282000000, 0x30 }, 351 { 580000000, 0x30 }, 513 { 165500000, 0x34, 0x30 }, 517 { 248500000, 0x30, 0x20 }, 553 { 146500000, 0xBC, 0x30 }, 705 { 422000000, 0x30 }, 735 { 704000000, 0x30 }, 780 { 70100000, 0x01, 40 }, [all …]
|
/openbmc/linux/arch/alpha/include/asm/ |
H A D | core_marvel.h | 137 io7_csr IO_ASIC_REV; /* 0x30.0000 */ 141 io7_csr PO7_RST2; /* 0x30.0100 */ 146 io7_csr IO7_ACC_CLUMP; /* 0x30.0300 */ 150 io7_csr IO7_UPH_TO; /* 0x30.0400 */ 154 io7_csr PO7_MONCTL; /* 0x30.0500 */ 158 io7_csr PO7_SCRATCH; /* 0x30.0600 */ 162 io7_csr PO7_PMASK; /* 0x30.0700 */ 166 io7_csr PO7_ERROR_SUM; /* 0x30.2000 */ 170 io7_csr PO7_UNCRR_SYM; /* 0x30.2100 */ 173 io7_csr PO7_UGBGE_SYM; /* 0x30.2200 */ [all …]
|
/openbmc/linux/drivers/edac/ |
H A D | amd64_edac.h | 131 * F15 M30h D18F1x2[4C:40] 258 #define UMCCH_ADDR_MASK_SEC_DDR5 0x30 259 #define UMCCH_ADDR_CFG 0x30 289 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers 356 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ 421 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; in get_dram_base() 431 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; in get_dram_limit() 441 if (pvt->fam == 0x15 && pvt->model >= 0x30) in dct_sel_interleave_addr() 503 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in dram_intlv_en() 513 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in dhar_valid() [all …]
|
/openbmc/qemu/tests/qtest/ |
H A D | cmsdk-apb-dualtimer-test.c | 20 /* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick */ 35 #define TIMER2RIS 0x30 58 clock_step(500 * 40 + 1); in test_dualtimer() 63 clock_step(500 * 40); in test_dualtimer() 71 clock_step(40); in test_dualtimer() 86 /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */ in test_prescale() 93 clock_step(40 * 256 * 501); in test_prescale() 98 clock_step(40 * 256 * 500); in test_prescale() 103 clock_step(40 * 256); in test_prescale()
|
H A D | boot-serial-test.c | 58 0x30, 0x60, 0x00, 0x04, /* addik r3,r0,4 */ 59 0x30, 0x80, 0x00, 0x54, /* addik r4,r0,'T' */ 66 0x00, 0x10, 0x60, 0x30, /* addik r3,r0,0x1000 */ 67 0x54, 0x00, 0x80, 0x30, /* addik r4,r0,'T' */ 73 0x08, 0x30, 0x9f, 0xe5, /* ldr r3,[pc,#8] Get base */ 116 0x0a, 0x4b, /* ldr r3, [pc, #40] Get GPIOA */ 155 { "ppc", "40p", "-vga none -boot d", "Trying cd:," }, 160 { "ppc64", "40p", "-m 192", "Memory: 192M" },
|
/openbmc/u-boot/arch/x86/dts/ |
H A D | chromebook_link.dts | 181 gpio-offset = <0x30 4>; 189 gpio-offset = <0x30 9>; 196 gpio-offset = <0x30 10>; 203 gpio-offset = <0x30 11>; 209 gpio-offset = <0x30 25>; 215 gpio-offset = <0x30 28>; 248 20 08 3c 3c 01 40 83 81 284 f0 0a 3c 3c 01 40 83 01 319 20 08 3c 3c 01 40 83 05 456 reg = <0x30 0x10>;
|
/openbmc/linux/drivers/gpu/host1x/ |
H A D | dev.c | 148 .offset = 0x30, 154 .offset = 0x30, 166 .dma_mask = DMA_BIT_MASK(40), 178 .offset = 0x30, 184 .offset = 0x30, 190 .offset = 0x30, 202 .dma_mask = DMA_BIT_MASK(40), 220 .offset = 0x30, 221 .limit = 0x30 232 .offset = 0x30, [all …]
|
/openbmc/linux/arch/mips/ar7/ |
H A D | irq.c | 26 #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */ 59 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); in ar7_unmask_sec_irq() 64 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); in ar7_mask_sec_irq() 69 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); in ar7_ack_sec_irq() 101 for (i = 0; i < 40; i++) { in ar7_irq_init() 108 irq_set_chip_and_handler(base + i + 40, in ar7_irq_init() 147 do_IRQ(ar7_irq_base + i + 40); in ar7_cascade()
|
/openbmc/linux/drivers/clk/uniphier/ |
H A D | clk-uniphier-mio.c | 17 UNIPHIER_CLK_FACTOR("sd-40m", -1, "sd-200m", 1, 5), \ 33 "sd-40m", \ 38 .reg = 0x30 + 0x200 * (ch), \
|
/openbmc/linux/Documentation/driver-api/media/drivers/ |
H A D | tuners.rst | 13 - P= PHILIPS_API (VHF_LO=0xA0, VHF_HI=0x90, UHF=0x30, radio=0x04) 82 40x2: Tuner (5V/33V), TEMIC_API. 83 40x6: Tuner 5V 85 40x9: Tuner+FM compact 97 Note: Only 40x2 series has TEMIC_API, all newer tuners have PHILIPS_API.
|
/openbmc/linux/samples/hid/ |
H A D | hid_mouse.bpf.c | 99 * 0x09, 0x30, // Usage (X) 38 in BPF_PROG() 100 * 0x09, 0x31, // Usage (Y) 40 in BPF_PROG() 107 data[41] = 0x30; in BPF_PROG()
|
/openbmc/u-boot/arch/arm/include/asm/arch-tegra20/ |
H A D | mc.h | 24 u32 mc_gart_error_req; /* offset 0x30 */ 31 u32 reserved4[40]; /* offset 0x60 - 0xFC */
|
/openbmc/linux/drivers/video/fbdev/sis/ |
H A D | sis.h | 90 #define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 65x, 740, 661, 741 */ 128 #define DAC2_ADR (0x16-0x30) 129 #define DAC2_DATA (0x17-0x30) 130 #define VB_PART1_ADR (0x04-0x30) 131 #define VB_PART1_DATA (0x05-0x30) 132 #define VB_PART2_ADR (0x10-0x30) 133 #define VB_PART2_DATA (0x11-0x30) 134 #define VB_PART3_ADR (0x12-0x30) 135 #define VB_PART3_DATA (0x13-0x30) 136 #define VB_PART4_ADR (0x14-0x30) [all …]
|
/openbmc/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm7445.dtsi | 72 serial@40ab00 { 99 irq0_intc: interrupt-controller@40a780 { 127 reg = <0x3e1000 0x30>; 137 reg = <0x410640 0x30>; 200 upg_gio: gpio@40a700 {
|
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/ |
H A D | adpll.txt | 20 adpll_mpu_ck: adpll@40 { 35 reg = <0x80 0x30>;
|