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/openbmc/linux/drivers/pci/controller/
H A Dpci-v3-semi.c3 * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
100 #define V3_LB_ISTAT_PCI_PERR BIT(3)
127 * This is the value applied to C/BE[3:1], with bit 0 always held 0
137 #define V3_PCI_BASE_M_PREFETCH BIT(3)
138 #define V3_PCI_BASE_M_TYPE (3 << 1)
144 #define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
145 #define V3_PCI_MAP_M_SWAP (3 << 8)
152 #define V3_LB_BASE_SWAP (3 << 8)
154 #define V3_LB_BASE_PREFETCH BIT(3)
160 #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
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/openbmc/linux/lib/
H A Dsiphash.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 * and HalfSipHash1-3/SipHash1-3 for an insecure PRF only suitable for
20 #define SIPROUND SIPHASH_PERMUTATION(v0, v1, v2, v3)
26 u64 v3 = SIPHASH_CONST_3; \
28 v3 ^= key->key[1]; \
34 v3 ^= b; \
43 return (v0 ^ v1) ^ (v2 ^ v3);
54 v3 ^= m; in __siphash_aligned()
69 case 3: b |= ((u64)end[2]) << 16; fallthrough; in __siphash_aligned()
87 v3 ^= m; in __siphash_unaligned()
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/openbmc/linux/arch/s390/include/asm/
H A Dvx-insn-asm.h40 \opd = 3
103 .ifc \vxr,%v3
104 \opd = 3
200 * @v3: Third vector register designated operand
203 .macro RXB rxb v1 v2=0 v3=0 v4=0
211 .if \v3 & 0x10
224 * @v3: Third vector register designated operand (for RXB)
227 .macro MRXB m v1 v2=0 v3=0 v4=0
229 RXB rxb, \v1, \v2, \v3, \v4
239 * @v3: Third vector register designated operand (for RXB)
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/openbmc/linux/arch/arm64/crypto/
H A Dchacha-neon-core.S32 * registers v0-v3. It performs matrix operations on four words in parallel,
47 eor v3.16b, v3.16b, v0.16b
48 rev32 v3.8h, v3.8h
51 add v2.4s, v2.4s, v3.4s
58 eor v3.16b, v3.16b, v0.16b
59 tbl v3.16b, {v3.16b}, v12.16b
62 add v2.4s, v2.4s, v3.4s
67 // x1 = shuffle32(x1, MASK(0, 3, 2, 1))
69 // x2 = shuffle32(x2, MASK(1, 0, 3, 2))
71 // x3 = shuffle32(x3, MASK(2, 1, 0, 3))
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H A Daes-ce-core.S17 bne 3f
18 mov v3.16b, v1.16b
21 ld1 {v3.4s}, [x0], #16
25 aese v0.16b, v3.16b
27 3: ld1 {v2.4s}, [x0], #16
28 subs w3, w3, #3
31 ld1 {v3.4s}, [x0], #16
34 eor v0.16b, v0.16b, v3.16b
45 bne 3f
46 mov v3.16b, v1.16b
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H A Dsm4-ce-core.S17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
42 .align 3
64 sm4ekey v3.4s, v2.4s, v27.4s;
65 sm4ekey v4.4s, v3.4s, v28.4s;
73 st1 {v0.16b-v3.16b}, [x1], #64;
80 tbl v20.16b, {v3.16b}, v24.16b
91 .align 3
107 .align 3
121 ld1 {v0.16b-v3.16b}, [x2], #64;
124 SM4_CRYPT_BLK8(v0, v1, v2, v3, v4, v5, v6, v7);
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H A Daes-ce-ccm-core.S31 1: ld1 {v3.4s}, [x4] /* load first round key */
38 mov v5.16b, v3.16b
40 2: mov v4.16b, v3.16b
42 3: aese v0.16b, v4.16b
44 4: ld1 {v3.4s}, [x6], #16 /* load next round key */
48 subs w7, w7, #3
49 aese v0.16b, v3.16b
52 bpl 3b
90 ld1 {v3.4s}, [x2], #16 /* load first round key */
96 bne 3f
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H A Dsm3-ce-core.S12 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
65 round \ab, \s0, v12, v11, 3
89 0: ld1 {v0.16b-v3.16b}, [x1], #64
98 CPU_LE( rev32 v3.16b, v3.16b )
102 qround a, v0, v1, v2, v3, v4
103 qround a, v1, v2, v3, v4, v0
104 qround a, v2, v3, v4, v0, v1
105 qround a, v3, v4, v0, v1, v2
109 qround b, v4, v0, v1, v2, v3
110 qround b, v0, v1, v2, v3, v4
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H A Dsm4-neon-core.S140 ROUND4(3, b3, b0, b1, b2); \
238 ROUND8(3, b3, b0, b1, b2, b7, b4, b5, b6); \
259 .align 3
273 ld4 {v0.4s-v3.4s}, [x2], #64
276 SM4_CRYPT_BLK8(v0, v1, v2, v3, v4, v5, v6, v7)
278 st1 {v0.16b-v3.16b}, [x1], #64
291 ld4 {v0.4s-v3.4s}, [x2], #64
293 SM4_CRYPT_BLK4(v0, v1, v2, v3)
295 st1 {v0.16b-v3.16b}, [x1], #64
308 transpose_4x4(v0, v1, v2, v3)
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H A Dsm4-ce-gcm-core.S18 .irp b, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31
236 /* can be the same as input v0-v3 */
240 #define RR7 v3
261 .align 3
285 /* H ^ 3 */
298 .align 3
322 ld1 {v0.16b-v3.16b}, [x2], #64
327 rbit v3.16b, v3.16b
331 * (in1) * H^3 => rr2:rr3
340 RR6, RR7, v3, RH1, RTMP6, RTMP7)
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/openbmc/qemu/target/s390x/tcg/
H A Dvec_string_helper.c43 return (c0 ? clz64(c0) : clz64(c1) + 64) >> 3; in match_index()
78 static int vfae(void *v1, const void *v2, const void *v3, bool in, in vfae() argument
90 b0 = s390_vec_read_element64(v3, 0); in vfae()
91 b1 = s390_vec_read_element64(v3, 1); in vfae()
127 return 3; /* no match */ in vfae()
137 void HELPER(gvec_vfae##BITS)(void *v1, const void *v2, const void *v3, \
140 const bool in = extract32(simd_data(desc), 3, 1); \
144 vfae(v1, v2, v3, in, rt, zs, MO_##BITS); \
151 void HELPER(gvec_vfae_cc##BITS)(void *v1, const void *v2, const void *v3, \
154 const bool in = extract32(simd_data(desc), 3, 1); \
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H A Dtranslate_vx.c.inc57 #define FPF_LONG 3
203 #define gen_gvec_3(v1, v2, v3, gen) \
205 vec_full_reg_offset(v3), 16, 16, gen)
206 #define gen_gvec_3_ool(v1, v2, v3, data, fn) \
208 vec_full_reg_offset(v3), 16, 16, data, fn)
209 #define gen_gvec_3_ptr(v1, v2, v3, ptr, data, fn) \
211 vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
212 #define gen_gvec_3i(v1, v2, v3, c, gen) \
214 vec_full_reg_offset(v3), 16, 16, c, gen)
215 #define gen_gvec_4(v1, v2, v3, v4, gen) \
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H A Dvec_helper.c22 void HELPER(gvec_vbperm)(void *v1, const void *v2, const void *v3, in HELPER()
30 const uint8_t bit_nr = s390_vec_read_element8(v3, i); in HELPER()
40 s390_vec_write_element16(&tmp, 3, result); in HELPER()
71 const S390Vector *v3, vpk##BITS##_fn fn) \
82 src = s390_vec_read_element##BITS(v3, i - (128 / BITS)); \
98 void HELPER(gvec_vpk##BITS)(void *v1, const void *v2, const void *v3, \
101 vpk##BITS##_hfn(v1, v2, v3, vpk##BITS##e); \
119 void HELPER(gvec_vpks##BITS)(void *v1, const void *v2, const void *v3, \
122 vpk##BITS##_hfn(v1, v2, v3, vpks##BITS##e); \
124 void HELPER(gvec_vpks_cc##BITS)(void *v1, const void *v2, const void *v3, \
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H A Dvec_fpu_helper.c231 const bool se = extract32(simd_data(desc), 3, 1); \
260 static void vop32_3(S390Vector *v1, const S390Vector *v2, const S390Vector *v3, in vop32_3() argument
270 const float32 b = s390_vec_read_float32(v3, i); in vop32_3()
283 static void vop64_3(S390Vector *v1, const S390Vector *v2, const S390Vector *v3, in vop64_3() argument
293 const float64 b = s390_vec_read_float64(v3, i); in vop64_3()
306 static void vop128_3(S390Vector *v1, const S390Vector *v2, const S390Vector *v3, in vop128_3() argument
311 const float128 b = s390_vec_read_float128(v3); in vop128_3()
322 void HELPER(gvec_##NAME##BITS)(void *v1, const void *v2, const void *v3, \
325 const bool se = extract32(simd_data(desc), 3, 1); \
327 vop##BITS##_3(v1, v2, v3, env, se, float##BITS##_##OP, GETPC()); \
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/openbmc/qemu/tests/tcg/s390x/
H A Dvrep.c28 vrep(S390Vector *v1, const S390Vector *v3, const uint16_t i2, const uint8_t m4) in vrep() argument
32 asm("vrep %[v1],%[v3],%[i2],%[m4]\n" in vrep()
35 : [v3] "v" (v3->v) in vrep()
44 S390Vector v3 = {.d[0] = 1, .d[1] = 2}; in main() local
55 assert(vrep(&v1, &v3, 7, 0) == -1); in main()
59 assert(vrep(&v1, &v3, 7, 1) == -1); in main()
63 assert(vrep(&v1, &v3, 1, 2) == -1); in main()
67 assert(vrep(&v1, &v3, 1, 3) == -1); in main()
71 assert(vrep(&v1, &v3, 0x10, 0) == SIGILL); in main()
72 assert(vrep(&v1, &v3, 0x101, 0) == SIGILL); in main()
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H A Dvxeh2_vstrs.c13 vstrs(S390Vector *v1, const S390Vector *v2, const S390Vector *v3, in vstrs() argument
18 asm("vstrs %[v1],%[v2],%[v3],%[v4],%[m5],%[m6]\n" in vstrs()
23 , [v3] "v" (v3->v) in vstrs()
29 return (cc >> 28) & 3; in vstrs()
36 S390Vector v3 = {.d[0] = 0x205e410000000000ULL, .d[1] = 0}; in test_ignored_match() local
37 S390Vector v4 = {.d[0] = 3, .d[1] = 0}; in test_ignored_match()
39 assert(vstrs(&v1, &v2, &v3, &v4, 0, 2) == 1); in test_ignored_match()
48 S390Vector v3 = {.d[0] = 0, .d[1] = 0}; in test_empty_needle() local
51 assert(vstrs(&v1, &v2, &v3, &v4, 0, 0) == 2); in test_empty_needle()
60 S390Vector v3 = {.d[0] = 0, .d[1] = 0}; in test_max_length() local
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/openbmc/linux/Documentation/devicetree/bindings/hwmon/
H A Dltc2990.txt15 2: V1-V2, V3, V4
16 3: TR1, V3, V4
17 4: TR1, V3-V4
19 6: V1-V2, V3-V4
20 7: V1, V2, V3, V4
22 The second integer defines the bits 4..3 in the control register. This
27 2: TR2, V3 or V3-V4 only per mode
28 3: All measurements per mode
35 lltc,meas-mode = <7 3>; /* V1, V2, V3, V4 */
/openbmc/linux/include/uapi/linux/
H A Dnfs.h34 #define NFS_MNT3_VERSION 3
47 NFS_OK = 0, /* v2 v3 v4 */
48 NFSERR_PERM = 1, /* v2 v3 v4 */
49 NFSERR_NOENT = 2, /* v2 v3 v4 */
50 NFSERR_IO = 5, /* v2 v3 v4 */
51 NFSERR_NXIO = 6, /* v2 v3 v4 */
52 NFSERR_EAGAIN = 11, /* v2 v3 */
53 NFSERR_ACCES = 13, /* v2 v3 v4 */
54 NFSERR_EXIST = 17, /* v2 v3 v4 */
55 NFSERR_XDEV = 18, /* v3 v4 */
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/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dsys_proto.h45 { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
51 { 0x01, 0x1f, "I2C #0, master, 3V3" },
53 { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
55 { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
56 { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
57 { 0x04, 0x1f, "NAND, 3V3" },
60 { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
61 { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
62 { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
64 { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dnvidia,tegra20-sdhci.yaml122 nvidia,pad-autocal-pull-down-offset-3v3:
127 nvidia,pad-autocal-pull-down-offset-3v3-timeout:
150 nvidia,pad-autocal-pull-up-offset-3v3:
162 nvidia,pad-autocal-pull-up-offset-3v3-timeout:
228 - const: sdmmc-3v3
232 - const: sdmmc-3v3-drv
237 - const: sdmmc-3v3-drv
257 - const: sdmmc-3v3
296 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
297 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
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/openbmc/phosphor-host-ipmid/test/message/
H A Dpack.cpp86 // v1 will occupy [2:0], v2 will occupy [7:3] in TEST()
103 // [v8, v7, v6, v5, v4, v3, v2, v1] in TEST()
106 bool v4 = true, v3 = false, v2 = false, v1 = true; in TEST() local
107 p.pack(v1, v2, v3, v4, v5, v6, v7, v8); in TEST()
132 // v1 will occupy [2:0], v2 will occupy [7:3] in TEST()
134 std::bitset<3> v1(0x1); in TEST()
192 // v[3][7:0] v[3][15:9] v[3][23:16] v[3][31:24] in TEST()
212 // v[3][7:0] v[3][15:9] v[3][23:16] v[3][31:24] in TEST()
339 // v1[7:0] v2[7:0] v2[15:8] v3[7:0] v3[15:8] v3[23:16] v3[31:24] in TEST()
345 uint32_t v3 = 0x44332211; in TEST() local
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/openbmc/qemu/hw/sd/
H A Dsdhci-internal.h46 #define SDHC_TRNS_ACMD23 0x0008 /* since v3 */
53 #define SDHC_CMD_RSP_WITH_BUSY (3 << 0)
67 /* ROC Response Register 3 0x0 */
110 FIELD(SDHC_PWRCON, BUS_VOLTAGE, 1, 3);
194 /* Host Control Register 2 (since v3) */
196 FIELD(SDHC_HOSTCTL2, UHS_MODE_SEL, 0, 3);
197 FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */
214 FIELD(SDHC_CAPAB, EMBEDDED_8BIT, 18, 1); /* since v3 */
225 FIELD(SDHC_CAPAB, ASYNC_INT, 29, 1); /* since v3 */
226 FIELD(SDHC_CAPAB, SLOT_TYPE, 30, 2); /* since v3 */
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/openbmc/linux/arch/powerpc/lib/
H A Dxor_vmx.c33 V##_3 = V[3]; \
41 V[3] = V##_3; \
78 DEFINE(v3); in __xor_altivec_3()
84 LOAD(v3); in __xor_altivec_3()
86 XOR(v1, v3); in __xor_altivec_3()
91 v3 += 4; in __xor_altivec_3()
103 DEFINE(v3); in __xor_altivec_4()
110 LOAD(v3); in __xor_altivec_4()
113 XOR(v3, v4); in __xor_altivec_4()
114 XOR(v1, v3); in __xor_altivec_4()
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dv3-v360epc-pci.txt1 V3 Semiconductor V360 EPC PCI bridge
7 "v3,v360epc-pci"
8 "arm,integrator-ap-pci", "v3,v360epc-pci"
10 first the base address of the V3 host bridge controller, 64KB
12 - interrupts: should contain a reference to the V3 error interrupt
29 operate the V3 host bridge.
34 compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
37 #address-cells = <3>;
58 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
63 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
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/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-d4xx.rst20 types are MetadataId_CaptureStats (ID 3), MetadataId_CameraExtrinsics (ID 4),
29 This document implements Intel Configuration version 3 [9_].
51 2 and 3. The version number will be incremented when new fields are
77 * - __u8 Emitter mode (v3 only) (__u32 Laser mode for v1) [8_]
79 * - __u8 RFU byte (v3 only)
81 * - __u16 LED Power (v3 only)
93 - A bitmask of flags: see [3_] below
110 - Size in bytes, include ID (v1:36, v3:40)
133 * - __u16 Calibration count (v3 only)
135 * - __u8 GPIO input data (v3 only)
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