Lines Matching +full:3 +full:v3
46 #define SDHC_TRNS_ACMD23 0x0008 /* since v3 */
53 #define SDHC_CMD_RSP_WITH_BUSY (3 << 0)
67 /* ROC Response Register 3 0x0 */
110 FIELD(SDHC_PWRCON, BUS_VOLTAGE, 1, 3);
194 /* Host Control Register 2 (since v3) */
196 FIELD(SDHC_HOSTCTL2, UHS_MODE_SEL, 0, 3);
197 FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */
214 FIELD(SDHC_CAPAB, EMBEDDED_8BIT, 18, 1); /* since v3 */
225 FIELD(SDHC_CAPAB, ASYNC_INT, 29, 1); /* since v3 */
226 FIELD(SDHC_CAPAB, SLOT_TYPE, 30, 2); /* since v3 */
227 FIELD(SDHC_CAPAB, BUS_SPEED, 32, 3); /* since v3 */
229 FIELD(SDHC_CAPAB, DRIVER_STRENGTH, 36, 3); /* since v3 */
230 FIELD(SDHC_CAPAB, DRIVER_TYPE_A, 36, 1); /* since v3 */
231 FIELD(SDHC_CAPAB, DRIVER_TYPE_C, 37, 1); /* since v3 */
232 FIELD(SDHC_CAPAB, DRIVER_TYPE_D, 38, 1); /* since v3 */
233 FIELD(SDHC_CAPAB, TIMER_RETUNING, 40, 4); /* since v3 */
234 FIELD(SDHC_CAPAB, SDR50_TUNING, 45, 1); /* since v3 */
235 FIELD(SDHC_CAPAB, RETUNING_MODE, 46, 2); /* since v3 */
236 FIELD(SDHC_CAPAB, CLOCK_MULT, 48, 8); /* since v3 */
257 #define SDHC_ADMAERR_STATE_ST_TFR (3 << 0)
258 #define SDHC_ADMAERR_STATE_MASK (3 << 0)
264 #define SDHC_ADMA_ATTR_ACT_LINK (3 << 4)
281 #define SDHC_CMD_RESPONSE (3 << 0)