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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt76x8-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt76x8-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt76x8-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
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/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt76x8.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "pinctrl-mtmips.h"
39 FUNC("sdxc d6", 3, 19, 1),
40 FUNC("utif", 2, 19, 1),
41 FUNC("gpio", 1, 19, 1),
42 FUNC("pwm1", 0, 19, 1),
46 FUNC("sdxc d7", 3, 18, 1),
47 FUNC("utif", 2, 18, 1),
48 FUNC("gpio", 1, 18, 1),
49 FUNC("pwm0", 0, 18, 1),
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
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H A Dt102xqds.c1 // SPDX-License-Identifier: GPL-2.0+
30 struct cpu_type *cpu = gd->arch.cpu; in checkboard()
35 printf("Board: %sQDS, ", cpu->name); in checkboard()
37 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); in checkboard()
79 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); in select_i2c_ch_pca9547()
94 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & in board_mux_lane_to_slot()
148 return -1; in board_mux_lane_to_slot()
180 if (hwconfig_arg_cmp("adaptor", "sdxc")) in board_mux_setup()
193 i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1); in board_retimer_ds125df111_init()
195 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1); in board_retimer_ds125df111_init()
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/openbmc/linux/include/linux/mmc/
H A Dsd.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
26 #define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
37 #define SD_OCR_S18R (1 << 24) /* 1.8V switching request */
39 #define SD_OCR_XPC (1 << 28) /* SDXC power control */
40 #define SD_OCR_CCS (1 << 30) /* Card Capacity Status */
45 * [31] Check (0) or switch (1)
52 * [3:0] Function group 1
67 #define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
68 #define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
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/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
/openbmc/u-boot/board/freescale/t208xqds/
H A DREADME1 The T2080QDS is a high-performance computing evaluation, development and
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
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/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME2 --------
9 personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
16 The board is re-designed T1040RDB board with following changes :
17 - Support of DDR4 memory and some enhancements
20 The board is re-designed T1040RDB board with following changes :
21 - Support of DDR4 memory
22 - Support for 0x86 serdes protocol which can support following interfaces
23 - 2 RGMII's on DTSEC4, DTSEC5
24 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
27 -------------------------------------------------------------------------
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/openbmc/linux/drivers/clk/x86/
H A Dclk-lgm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
8 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/intel,lgm-clk.h>
13 #include "clk-cgu.h"
31 #define G_LEDC0_SHIFT 1
62 #define G_PCIE10_SHIFT 1
117 #define CLK_NR_CLKS (LGM_GCLK_USB2 + 1)
121 * It's more efficient to provide an explicit table due to non-linear
125 { .val = 0, .div = 1 },
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/openbmc/u-boot/drivers/mmc/
H A DKconfig31 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
32 and non-removable (e.g. eMMC chip) devices are supported. These
33 appear as block devices in U-Boot and can support filesystems such
42 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
43 and non-removable (e.g. eMMC chip) devices are supported. These
44 appear as block devices in U-Boot and can support filesystems such
102 The Ultra High Speed (UHS) bus is available on some SDHC and SDXC
110 The Ultra High Speed (UHS) bus is available on some SDHC and SDXC
161 you are reading this help text, you most likely have no idea :-)
213 as removeable SD and micro-SD cards.
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/openbmc/linux/arch/mips/boot/dts/ralink/
H A Dmt7628a.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7628a-soc";
9 #address-cells = <1>;
10 #size-cells = <0>;
19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
24 cpuintc: interrupt-controller {
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/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/mmc/core/
H A Dcard.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #define mmc_card_name(c) ((c)->cid.prod_name)
16 #define mmc_card_id(c) (dev_name(&(c)->dev))
20 #define MMC_STATE_PRESENT (1<<0) /* present in sysfs */
21 #define MMC_STATE_READONLY (1<<1) /* card is read-only */
22 #define MMC_STATE_BLOCKADDR (1<<2) /* card uses block-addressing */
23 #define MMC_CARD_SDXC (1<<3) /* card is SDXC */
24 #define MMC_CARD_REMOVED (1<<4) /* card has been removed */
25 #define MMC_STATE_SUSPENDED (1<<5) /* card is suspended */
27 #define mmc_card_present(c) ((c)->state & MMC_STATE_PRESENT)
[all …]
H A Dbus.c1 // SPDX-License-Identifier: GPL-2.0-only
36 switch (card->type) { in type_show()
46 return -EFAULT; in type_show()
65 switch (card->type) { in mmc_bus_uevent()
90 card->cis.vendor, card->cis.device); in mmc_bus_uevent()
95 card->major_rev, card->minor_rev); in mmc_bus_uevent()
99 for (i = 0; i < card->num_info; i++) { in mmc_bus_uevent()
100 retval = add_uevent_var(env, "SDIO_INFO%u=%s", i+1, card->info[i]); in mmc_bus_uevent()
107 * SDIO (non-combo) cards are not handled by mmc_block driver and do not in mmc_bus_uevent()
128 struct mmc_driver *drv = to_mmc_driver(dev->driver); in mmc_bus_probe()
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H A Dsd.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2003-2004 Russell King, All Rights Reserved.
7 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
44 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
62 const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
63 const int __off = 3 - ((start) / 32); \
69 __res |= resp[__off-1] << ((32 - __shft) % 32); \
86 u32 *resp = card->raw_cid; in mmc_decode_cid()
92 add_device_randomness(&card->raw_cid, sizeof(card->raw_cid)); in mmc_decode_cid()
98 card->cid.manfid = UNSTUFF_BITS(resp, 120, 8); in mmc_decode_cid()
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc3 1. LS1043A
13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
[all …]
/openbmc/u-boot/board/freescale/t208xrdb/
H A DREADME1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
52 #define PHY_CTRL_ITAPDLY_SEL_MASK GENMASK(5, 1)
53 #define PHY_CTRL_ITAPDLY_SEL_SHIFT 1
64 #define PHY_CTRL_DLL_RDY_MASK BIT(1)
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/openbmc/qemu/hw/sd/
H A Dsd.c5 * eMMC emulation defined in "JEDEC Standard No. 84-A43"
9 * Copyright (c) 2018 Philippe Mathieu-Daudé <f4bug@amsat.org>
15 * 1. Redistributions of source code must retain the above copyright
40 #include "sysemu/block-backend.h"
46 #include "hw/qdev-properties.h"
47 #include "hw/qdev-properties-system.h"
48 #include "qemu/error-report.h"
51 #include "qemu/guest-random.h"
53 #include "sdmmc-internal.h"
56 //#define DEBUG_SD 1
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