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/openbmc/u-boot/board/freescale/common/p_corenet/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
16 MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/linux/fs/adfs/
H A Dadfs.h8 #define ADFS_FREE_FRAG 0
12 #define ADFS_FILETYPE_NONE ((u16)~0)
17 return (loadaddr & 0xfff00000) == 0xfff00000 ? in adfs_filetype()
18 (loadaddr >> 8) & 0xfff : ADFS_FILETYPE_NONE; in adfs_filetype()
21 #define ADFS_NDA_OWNER_READ (1 << 0)
49 return (ADFS_I(inode)->loadaddr & 0xfff00000) == 0xfff00000; in adfs_inode_is_stamped()
193 if (shift >= 0) in signed_asl()
223 return (void *)(dm[0].dm_bh->b_data + 4); in adfs_map_discrecord()
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Du-boot-nand_spl.lds14 . = 0xfff00000;
47 .bootpg ADDR(.text) + 0x1000 :
51 #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
53 #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
59 } = 0xffff
68 ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big");
/openbmc/linux/drivers/soc/fsl/
H A Dguts.c36 .svr = 0x82400000,
37 .mask = 0xfff00000,
41 .svr = 0x85200000,
42 .mask = 0xfff00000,
46 .svr = 0x85300000,
47 .mask = 0xfff00000,
51 .svr = 0x85400000,
52 .mask = 0xfff00000,
61 .svr = 0x87920000,
62 .mask = 0xffff0000,
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dvaddrs.h15 #define SRMMU_MAXMEM 0x0c000000
18 /* = 0x0fc000000 */
47 /* Leave one empty page between IO pages at 0xfd000000 and
50 #define FIXADDR_TOP (0xfcfff000UL)
56 #define SUN4M_IOBASE_VADDR 0xfd000000 /* Base for mapping pages */
57 #define IOBASE_VADDR 0xfe000000
58 #define IOBASE_END 0xfe600000
60 #define KADB_DEBUGGER_BEGVM 0xffc00000 /* Where kern debugger is in virt-mem */
61 #define KADB_DEBUGGER_ENDVM 0xffd00000
65 #define LINUX_OPPROM_BEGVM 0xffd00000
[all …]
/openbmc/linux/samples/bpf/
H A Dtcp_synrto_kern.c53 if (skops->local_ip6[0] == skops->remote_ip6[0] && in bpf_synrto()
54 (bpf_ntohl(skops->local_ip6[1]) & 0xfff00000) == in bpf_synrto()
55 (bpf_ntohl(skops->remote_ip6[1]) & 0xfff00000)) in bpf_synrto()
H A Dtcp_basertt_kern.c29 int rv = 0, n; in bpf_basertt()
43 skops->local_ip6[0] == skops->remote_ip6[0] && in bpf_basertt()
44 (bpf_ntohl(skops->local_ip6[1]) & 0xfff00000) == in bpf_basertt()
45 (bpf_ntohl(skops->remote_ip6[1]) & 0xfff00000)) { in bpf_basertt()
H A Dtcp_cong_kern.c28 int rv = 0; in bpf_cong()
51 skops->local_ip6[0] == skops->remote_ip6[0] && in bpf_cong()
52 (bpf_ntohl(skops->local_ip6[1]) & 0xfff00000) == in bpf_cong()
53 (bpf_ntohl(skops->remote_ip6[1]) & 0xfff00000)) { in bpf_cong()
H A Dtcp_clamp_kern.c31 int rv = 0; in bpf_clamp()
39 return 0; in bpf_clamp()
53 skops->local_ip6[0] == skops->remote_ip6[0] && in bpf_clamp()
54 (bpf_ntohl(skops->local_ip6[1]) & 0xfff00000) == in bpf_clamp()
55 (bpf_ntohl(skops->remote_ip6[1]) & 0xfff00000)) { in bpf_clamp()
/openbmc/u-boot/arch/x86/cpu/quark/
H A DKconfig45 default 0xfff00000
50 The default base address of 0xfff00000 indicates that the binary must
51 be located at offset 0 from the beginning of a 1MB flash device.
69 default 0x80000000
75 default 0xe0000000
79 default 0xfed1c000
85 default 0x1000
92 default 0x1010
99 default 0x1020
105 default 0x1080
[all …]
/openbmc/u-boot/board/armltd/integrator/
H A Dpci_v3.h23 #define V3_PCI_VENDOR 0x00000000
24 #define V3_PCI_DEVICE 0x00000002
25 #define V3_PCI_CMD 0x00000004
26 #define V3_PCI_STAT 0x00000006
27 #define V3_PCI_CC_REV 0x00000008
28 #define V3_PCI_HDR_CFG 0x0000000C
29 #define V3_PCI_IO_BASE 0x00000010
30 #define V3_PCI_BASE0 0x00000014
31 #define V3_PCI_BASE1 0x00000018
32 #define V3_PCI_SUB_VENDOR 0x0000002C
[all …]
/openbmc/linux/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/openbmc/u-boot/include/configs/
H A Damcore.h15 #define CONFIG_SYS_UART_PORT 0
21 "protect off 0xffc00000 0xffc1ffff; " \
22 "erase 0xffc00000 0xffc1ffff; " \
23 "cp.b 0x20000 0xffc00000 ${filesize}\0" \
25 "erase 0xffc20000 0xffefffff; " \
26 "cp.b 0x20000 0xffc20000 ${filesize}\0" \
28 "erase 0xfff00000 0xffffffff; " \
29 "cp.b 0x20000 0xfff00000 ${filesize}\0"
35 #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
37 #define CONFIG_SYS_MEMTEST_START 0x0
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dmp.c29 return 0; in cpu_status()
38 case 0: in cpu_disable()
49 return 0; in cpu_disable()
58 case 0: in is_core_disabled()
66 return 0; in is_core_disabled()
82 if ((u64)gd->ram_size > 0xfffff000) in determine_mp_bootpg()
83 return (0xfff00000); in determine_mp_bootpg()
122 write_bat(DBAT7, 0, 0); in setup_mp()
125 if (bootpg != 0xfff00000) in setup_mp()
126 out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 | in setup_mp()
/openbmc/qemu/hw/misc/
H A Dxlnx-versal-xramc.c20 #define XLNX_XRAM_CTRL_ERR_DEBUG 0
42 return 0; in xram_ien_prew()
52 return 0; in xram_ids_prew()
57 .reset = 0xf,
58 .rsvd = 0xfffffff0,
60 .rsvd = 0xfffff800,
61 .w1c = 0x7ff,
64 .reset = 0x7ff,
65 .rsvd = 0xfffff800,
66 .ro = 0x7ff,
[all …]
/openbmc/linux/arch/mips/loongson2ef/common/cs5536/
H A Dcs5536_acc.c17 u32 hi = 0, lo = value; in pci_acc_write_reg()
23 lo |= (0x03 << 8); in pci_acc_write_reg()
25 lo &= ~(0x03 << 8); in pci_acc_write_reg()
32 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; in pci_acc_write_reg()
42 } else if (value & 0x01) { in pci_acc_write_reg()
43 value &= 0xfffffffc; in pci_acc_write_reg()
44 hi = 0xA0000000 | ((value & 0x000ff000) >> 12); in pci_acc_write_reg()
45 lo = 0x000fff80 | ((value & 0x00000fff) << 20); in pci_acc_write_reg()
52 lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT); in pci_acc_write_reg()
65 u32 conf_data = 0; in pci_acc_read_reg()
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/vcap/
H A Dvcap_api_debugfs_kunit.c43 if (kslist->cnt > 0) { in test_val_keyset()
46 for (idx = 0; idx < kslist->cnt; idx++) { in test_val_keyset()
61 for (idx = 0; idx < kslist->cnt; idx++) { in test_val_keyset()
84 if (admin->vinst == 0 || admin->vinst == 2) in test_add_def_fields()
96 memset(admin->cache.keystream, 0, test_cache_erase_count); in test_cache_erase()
97 memset(admin->cache.maskstream, 0, test_cache_erase_count); in test_cache_erase()
98 memset(admin->cache.actionstream, 0, test_cache_erase_count); in test_cache_erase()
99 test_cache_erase_count = 0; in test_cache_erase()
123 for (idx = 0; idx < count; ++idx) { in test_cache_read()
124 pr_debug("%s:%d: keydata[%02d]: 0x%08x\n", __func__, in test_cache_read()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/openbmc/u-boot/board/freescale/t4qds/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
/openbmc/u-boot/board/intel/minnowmax/
H A DKconfig16 default 0xfff00000
26 default 0xe0000000
/openbmc/u-boot/board/intel/bayleybay/
H A DKconfig16 default 0xfff00000
26 default 0xe0000000
/openbmc/u-boot/board/freescale/t208xqds/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/u-boot/board/freescale/t208xrdb/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/u-boot/board/freescale/b4860qds/
H A Dtlb.c10 /* TLB 0 - for temp stack in cache */
11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
13 MAS3_SX|MAS3_SW|MAS3_SR, 0,
14 0, 0, BOOKE_PAGESZ_4K, 0),
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17 MAS3_SX|MAS3_SW|MAS3_SR, 0,
18 0, 0, BOOKE_PAGESZ_4K, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]

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