Searched +full:0 +full:xf8034000 (Results 1 – 13 of 13) sorted by relevance
39 reg = <0xf8034000 0x200>;43 ranges = <0x0 0xf8034000 0x800>;48 reg = <0x400 0x200>;51 pinctrl-0 = <&pinctrl_flx0_default>;53 #size-cells = <0>;58 flash@0 {60 reg = <0>;
45 reg = <0xf8034000 0x400>;
17 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */23 #define ATMEL_ID_USART0 5 /* USART 0 */27 #define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */30 #define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */31 #define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */33 #define ATMEL_ID_UART0 15 /* UART 0 */35 #define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */38 #define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */53 #define ATMEL_BASE_SPI0 0xf000000054 #define ATMEL_BASE_SPI1 0xf0004000[all …]
18 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */30 #define ATMEL_ID_USART0 12 /* USART 0 */36 #define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */39 #define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */42 #define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */56 #define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */70 #define ARCH_ID_SAMA5D3 0x8a5c07c071 #define ARCH_EXID_SAMA5D31 0x0044430072 #define ARCH_EXID_SAMA5D33 0x0041430073 #define ARCH_EXID_SAMA5D34 0x00414301[all …]
15 #define ATMEL_ID_FIQ 0 /* FIQ Interrupt */21 #define ATMEL_ID_USART0 6 /* USART 0 */23 #define ATMEL_ID_DMA0 8 /* DMA Controller 0 */40 #define ATMEL_ID_UART0 27 /* UART 0 */45 #define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */48 #define ATMEL_ID_MCI0 35 /* High Speed Multimedia Card Interface 0 */50 #define ATMEL_ID_SPI0 37 /* Serial Peripheral Interface 0 */53 #define ATMEL_ID_TC0 40 /* Timer Counter 0 (ch. 0, 1, 2) */61 #define ATMEL_ID_SSC0 48 /* Synchronous Serial Controller 0 */67 #define ATMEL_ID_GMAC0 54 /* Ethernet MAC 0 */[all …]
29 #size-cells = <0>;31 cpu@0 {34 reg = <0>;41 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;46 reg = <0x740000 0x1000>;62 reg = <0x73c000 0x1000>;78 reg = <0x20000000 0x20000000>;84 #clock-cells = <0>;85 clock-frequency = <0>;90 #clock-cells = <0>;[all …]
42 #size-cells = <0>;44 cpu@0 {47 reg = <0>;53 reg = <0x20000000 0x10000000>;59 #clock-cells = <0>;60 clock-frequency = <0>;65 #clock-cells = <0>;66 clock-frequency = <0>;72 reg = <0x00300000 0x8000>;75 ranges = <0 0x00300000 0x8000>;[all …]
44 #size-cells = <0>;46 cpu@0 {49 reg = <0>;55 reg = <0x20000000 0x10000000>;61 #clock-cells = <0>;62 clock-frequency = <0>;67 #clock-cells = <0>;68 clock-frequency = <0>;73 #clock-cells = <0>;80 reg = <0x00300000 0x8000>;[all …]
46 #size-cells = <0>;47 cpu@0 {50 reg = <0x0>;56 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;61 reg = <0x20000000 0x8000000>;67 #clock-cells = <0>;68 clock-frequency = <0>;73 #clock-cells = <0>;74 clock-frequency = <0>;79 #clock-cells = <0>;[all …]
37 #size-cells = <0>;39 cpu@0 {42 reg = <0>;48 reg = <0x20000000 0x10000000>;54 #clock-cells = <0>;59 #clock-cells = <0>;65 reg = <0x00300000 0x100000>;68 ranges = <0 0x00300000 0x100000>;79 #size-cells = <0>;81 reg = <0x00500000 0x100000[all …]
48 reg = <0x20000000 0x10000000>;54 #clock-cells = <0>;55 clock-frequency = <0>;60 #clock-cells = <0>;61 clock-frequency = <0>;67 reg = <0x00300000 0x8000>;88 reg = <0xfffff000 0x200>;94 reg = <0xffffe800 0x200>;101 reg = <0xfffffc00 0x200>;105 #size-cells = <0>;[all …]
51 reg = <0x20000000 0x10000000>;57 #clock-cells = <0>;58 clock-frequency = <0>;63 #clock-cells = <0>;64 clock-frequency = <0>;69 #clock-cells = <0>;76 reg = <0x00300000 0x8000>;97 reg = <0xfffff000 0x200>;103 reg = <0xffffe800 0x200>;110 reg = <0xfffffc00 0x200>;[all …]
45 #size-cells = <0>;46 cpu@0 {49 reg = <0x0>;55 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;59 reg = <0x20000000 0x8000000>;65 #clock-cells = <0>;66 clock-frequency = <0>;71 #clock-cells = <0>;72 clock-frequency = <0>;77 #clock-cells = <0>;[all …]