Home
last modified time | relevance | path

Searched +full:0 +full:xf01 (Results 1 – 25 of 42) sorted by relevance

12

/openbmc/linux/Documentation/devicetree/bindings/soc/ti/
H A Dkeystone-navigator-qmss.txt27 external link ram entries. If the address is specified as "0"
83 0 : None, i.e interrupt on list full only
123 queue-range = <0 0x4000>;
124 linkram0 = <0x100000 0x8000>;
125 linkram1 = <0x0 0x10000>;
132 managed-queues = <0 0x2000>;
133 reg = <0x2a40000 0x20000>,
134 <0x2a06000 0x400>,
135 <0x2a02000 0x1000>,
136 <0x2a03000 0x1000>,
[all …]
/openbmc/linux/arch/arm/boot/dts/calxeda/
H A Dhighbank.dts9 /memreserve/ 0x00000000 0x0001000;
19 #size-cells = <0>;
24 reg = <0x900>;
43 reg = <0x901>;
62 reg = <0x902>;
81 reg = <0x903>;
98 memory@0 {
101 reg = <0x00000000 0xff900000>;
105 ranges = <0x00000000 0x00000000 0xffffffff>;
109 reg = <0xfff00000 0x1000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,global_timer.yaml44 reg = <0x2c000600 0x20>;
45 interrupts = <1 13 0xf01>;
H A Darm,twd-timer.yaml54 reg = <0x2c000600 0x20>;
55 interrupts = <GIC_PPI 13 0xf01>;
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Darm,twd-wdt.yaml48 reg = <0x2c000620 0x20>;
49 interrupts = <GIC_PPI 14 0xf01>;
/openbmc/u-boot/arch/arm/dts/
H A Dbcm2836.dtsi7 ranges = <0x7e000000 0x3f000000 0x1000000>,
8 <0x40000000 0x40000000 0x00001000>;
9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 reg = <0x40000000 0x100>;
29 interrupts = <0>, // PHYS_SECURE_PPI
38 #size-cells = <0>;
41 v7_cpu0: cpu@0 {
44 reg = <0xf00>;
51 reg = <0xf01>;
58 reg = <0xf02>;
[all …]
H A Dls1021a.dtsi27 #size-cells = <0>;
32 reg = <0xf00>;
39 reg = <0xf01>;
70 reg = <0x1401000 0x1000>,
71 <0x1402000 0x1000>,
72 <0x1404000 0x2000>,
73 <0x1406000 0x2000>;
80 reg = <0x1530000 0x10000>;
86 reg = <0x1ee0000 0x10000>;
92 reg = <0x1560000 0x10000>;
[all …]
H A Drk3036.dtsi29 reg = <0x60000000 0x40000000>;
41 #size-cells = <0>;
47 reg = <0xf00>;
60 reg = <0xf01>;
73 reg = <0x20078000 0x4000>;
75 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
87 #clock-cells = <0>;
102 reg = <0x20000000 0x1000>;
112 reg = <0x20060000 0x100>;
120 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
[all …]
H A Drk322x.dtsi29 #size-cells = <0>;
34 reg = <0xf00>;
48 reg = <0xf01>;
55 reg = <0xf02>;
62 reg = <0xf03>;
75 reg = <0x110f0000 0x4000>;
76 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
107 #clock-cells = <0>;
112 reg = <0x10080000 0x9000>;
115 ranges = <0 0x10080000 0x9000>;
[all …]
H A Dsocfpga.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0>;
43 interrupts = <0 176 4>, <0 177 4>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
[all …]
/openbmc/linux/arch/arm/boot/dts/socionext/
H A Dmilbeaut-m10v.dtsi15 #size-cells = <0>;
20 reg = <0xf00>;
25 reg = <0xf01>;
30 reg = <0xf02>;
35 reg = <0xf03>;
64 reg = <0x1d001000 0x1000>,
65 <0x1d002000 0x1000>; /* CPU I/f base and size */
71 reg = <0x1d021000 0x1000>;
77 reg = <0x1e000050 0x20>;
78 interrupts = <0 91 4>;
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dpsci.S14 #define RCPM_TWAITSR 0x04C
16 #define SCFG_CORE0_SFT_RST 0x130
17 #define SCFG_CORESRENCR 0x204
19 #define DCFG_CCSR_RSTCR 0x0B0
20 #define DCFG_CCSR_RSTCR_RESET_REQ 0x2
21 #define DCFG_CCSR_BRR 0x0E4
22 #define DCFG_CCSR_SCRATCHRW1 0x200
24 #define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0
25 #define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0
26 #define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2836.dtsi9 ranges = <0x7e000000 0x3f000000 0x1000000>,
10 <0x40000000 0x40000000 0x00001000>;
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
15 reg = <0x40000000 0x100>;
31 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
40 #size-cells = <0>;
51 v7_cpu0: cpu@0 {
54 reg = <0xf00>;
56 d-cache-size = <0x8000>;
59 i-cache-size = <0x8000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2e-netcp.dtsi15 queue-range = <0 0x2000>;
16 linkram0 = <0x100000 0x4000>;
17 linkram1 = <0 0x10000>;
24 managed-queues = <0 0x2000>;
25 reg = <0x2a40000 0x20000>,
26 <0x2a06000 0x400>,
27 <0x2a02000 0x1000>,
28 <0x2a03000 0x1000>,
29 <0x23a80000 0x20000>,
30 <0x2a80000 0x20000>;
[all …]
H A Dkeystone-k2l-netcp.dtsi15 queue-range = <0 0x2000>;
16 linkram0 = <0x100000 0x4000>;
17 linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
24 managed-queues = <0 0x2000>;
25 reg = <0x2a40000 0x20000>,
26 <0x2a06000 0x400>,
27 <0x2a02000 0x1000>,
28 <0x2a03000 0x1000>,
29 <0x23a80000 0x20000>,
30 <0x2a80000 0x20000>;
[all …]
H A Dkeystone-k2hk-netcp.dtsi15 queue-range = <0 0x4000>;
16 linkram0 = <0x100000 0x8000>;
17 linkram1 = <0x0 0x10000>;
24 managed-queues = <0 0x2000>;
25 reg = <0x2a40000 0x20000>,
26 <0x2a06000 0x400>,
27 <0x2a02000 0x1000>,
28 <0x2a03000 0x1000>,
29 <0x23a80000 0x20000>,
30 <0x2a80000 0x20000>;
[all …]
/openbmc/linux/include/linux/mlx4/
H A Dcmd.h43 MLX4_CMD_SYS_EN = 0x1,
44 MLX4_CMD_SYS_DIS = 0x2,
45 MLX4_CMD_MAP_FA = 0xfff,
46 MLX4_CMD_UNMAP_FA = 0xffe,
47 MLX4_CMD_RUN_FW = 0xff6,
48 MLX4_CMD_MOD_STAT_CFG = 0x34,
49 MLX4_CMD_QUERY_DEV_CAP = 0x3,
50 MLX4_CMD_QUERY_FW = 0x4,
51 MLX4_CMD_ENABLE_LAM = 0xff8,
52 MLX4_CMD_DISABLE_LAM = 0xff7,
[all …]
/openbmc/linux/arch/arm/boot/dts/axis/
H A Dartpec6.dtsi55 #size-cells = <0>;
57 cpu0: cpu@0 {
60 reg = <0>;
74 reg = <0xf8000000 0x48>;
80 psci_version = <0x84000000>;
81 cpu_on = <0x84000003>;
82 system_reset = <0x84000009>;
87 reg = <0xfaf00000 0x58>;
92 #clock-cells = <0>;
98 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/hisilicon/
H A Dhisi-x5hd2.dtsi20 #address-cells = <0>;
23 reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
31 ranges = <0 0xf8000000 0x8000000>;
41 reg = <0x00002000 0x1000>;
43 interrupts = <0 24 4>;
55 reg = <0x00a29000 0x1000>;
57 interrupts = <0 25 4>;
64 reg = <0x00a2a000 0x1000>;
66 interrupts = <0 26 4>;
73 reg = <0x00a2b000 0x1000>;
[all …]
H A Dhi3620.dtsi27 #clock-cells = <0>;
34 #size-cells = <0>;
37 cpu@0 {
40 reg = <0x0>;
72 ranges = <0 0xfc000000 0x2000000>;
76 reg = <0x100000 0x100000>;
77 interrupts = <0 15 4>;
85 #address-cells = <0>;
88 reg = <0x1000 0x1000>, <0x100 0x100>;
95 ranges = <0 0x802000 0x1000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi28 #size-cells = <0>;
33 reg = <0xf00>;
41 reg = <0xf01>;
49 reg = <0xf02>;
57 reg = <0xf03>;
95 #clock-cells = <0>;
100 reg = <0xfe000000 0x20000>;
105 reg = <0xfe020000 0x1000>;
115 reg = <0xfe860000 0x20>;
120 reg = <0xfe860080 0x20>;
[all …]
H A Drk3036.dtsi34 #size-cells = <0>;
40 reg = <0xf00>;
53 reg = <0xf01>;
84 #clock-cells = <0>;
89 reg = <0x10080000 0x2000>;
92 ranges = <0 0x10080000 0x2000>;
94 smp-sram@0 {
96 reg = <0x00 0x10>;
102 reg = <0x10090000 0x10000>;
122 reg = <0x10108000 0x800>;
[all …]
H A Drk3128.dtsi29 #size-cells = <0>;
34 reg = <0xf00>;
47 reg = <0xf01>;
53 reg = <0xf02>;
59 reg = <0xf03>;
77 #clock-cells = <0>;
82 reg = <0x100a0000 0x1000>;
87 reg = <0x10139000 0x1000>,
88 <0x1013a000 0x1000>,
89 <0x1013c000 0x2000>,
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dstm32f746-pinfunc.h4 #define STM32F746_PA0_FUNC_GPIO 0x0
5 #define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32F746_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32F746_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32F746_PA0_FUNC_USART2_CTS 0x8
9 #define STM32F746_PA0_FUNC_UART4_TX 0x9
10 #define STM32F746_PA0_FUNC_SAI2_SD_B 0xb
11 #define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc
12 #define STM32F746_PA0_FUNC_EVENTOUT 0x10
13 #define STM32F746_PA0_FUNC_ANALOG 0x11
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10.dtsi15 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
35 interrupts = <0 124 4>, <0 125 4>;
37 reg = <0xff111000 0x1000>,
38 <0xff113000 0x1000>;
45 reg = <0xffffd000 0x1000>,
46 <0xffffc100 0x100>;
65 reg = <0xffda1000 0x1000>;
66 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
[all …]

12