/openbmc/u-boot/include/configs/ |
H A D | blanche.h | 15 #define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 16 #define STACK_AREA_SIZE 0x00100000 21 #define RCAR_GEN2_SDRAM_BASE 0x40000000 30 #define CONFIG_SH_QSPI_BASE 0xE6B10000 35 #define CONFIG_SYS_FLASH_BASE 0x00000000 36 #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
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/openbmc/linux/Documentation/devicetree/bindings/spi/ |
H A D | renesas,rspi.yaml | 145 reg = <0xe6b10000 0x2c>; 148 dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; 154 #size-cells = <0>;
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/openbmc/u-boot/board/renesas/gose/ |
H A D | gose_spl.c | 26 #define SD2CKCR 0xE615026C 27 #define SD_97500KHZ 0x7 38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait() 44 u32 r0 = 0; in spl_init_sys() 46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys() 47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys() 51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys() 53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys() 55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys() 56 "orr %0, #0x1800 \n" in spl_init_sys() [all …]
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/openbmc/u-boot/board/renesas/alt/ |
H A D | alt_spl.c | 26 #define SD1CKCR 0xE6150078 27 #define SD_97500KHZ 0x7 38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait() 44 u32 r0 = 0; in spl_init_sys() 46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys() 47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys() 51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys() 53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys() 55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys() 56 "orr %0, #0x1800 \n" in spl_init_sys() [all …]
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/openbmc/u-boot/board/renesas/koelsch/ |
H A D | koelsch_spl.c | 26 #define SD2CKCR 0xE615026C 27 #define SD_97500KHZ 0x7 37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait() 39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait() 42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait() 48 u32 r0 = 0; in spl_init_sys() 50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys() 51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys() 55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys() 57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys() [all …]
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/openbmc/u-boot/board/renesas/lager/ |
H A D | lager_spl.c | 26 #define SD2CKCR 0xE615026C 27 #define SD_97500KHZ 0x7 38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait() 44 u32 r0 = 0; in spl_init_sys() 46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys() 47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys() 51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys() 53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys() 55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys() 56 "orr %0, #0x1800 \n" in spl_init_sys() [all …]
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/openbmc/u-boot/board/renesas/silk/ |
H A D | silk_spl.c | 26 #define SD1CKCR 0xE6150078 27 #define SD_97500KHZ 0x7 38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait() 44 u32 r0 = 0; in spl_init_sys() 46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys() 47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys() 51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys() 53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys() 55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys() 56 "orr %0, #0x1800 \n" in spl_init_sys() [all …]
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/openbmc/u-boot/board/renesas/stout/ |
H A D | stout_spl.c | 26 #define SD2CKCR 0xE615026C 27 #define SD_97500KHZ 0x7 37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait() 39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait() 42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait() 48 u32 r0 = 0; in spl_init_sys() 50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys() 51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys() 55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys() 57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys() [all …]
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/openbmc/u-boot/board/renesas/porter/ |
H A D | porter_spl.c | 26 #define SD2CKCR 0xE615026C 27 #define SD_97500KHZ 0x7 37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait() 39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait() 42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait() 48 u32 r0 = 0; in spl_init_sys() 50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys() 51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys() 55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys() 57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys() [all …]
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/openbmc/u-boot/arch/arm/mach-rmobile/include/mach/ |
H A D | rcar-base.h | 14 #define RWDT_BASE 0xE6020000 15 #define SWDT_BASE 0xE6030000 16 #define LBSC_BASE 0xFEC00200 17 #define DBSC3_0_BASE 0xE6790000 18 #define DBSC3_1_BASE 0xE67A0000 19 #define TMU_BASE 0xE61E0000 20 #define GPIO5_BASE 0xE6055000 21 #define SH_QSPI_BASE 0xE6B10000 24 #define SCIF0_BASE 0xE6E60000 25 #define SCIF1_BASE 0xE6E68000 [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | r8a7792.dtsi | 39 #clock-cells = <0>; 41 clock-frequency = <0>; 46 #size-cells = <0>; 49 cpu0: cpu@0 { 52 reg = <0>; 69 L2_CA15: cache-controller-0 { 80 #clock-cells = <0>; 82 clock-frequency = <0>; 95 #clock-cells = <0>; 97 clock-frequency = <0>; [all …]
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H A D | r8a7794.dtsi | 34 * The external audio clocks are configured as 0 Hz fixed frequency 40 #clock-cells = <0>; 41 clock-frequency = <0>; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 50 #clock-cells = <0>; 51 clock-frequency = <0>; 57 #clock-cells = <0>; 59 clock-frequency = <0>; 64 #size-cells = <0>; [all …]
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H A D | r8a7793.dtsi | 32 * The external audio clocks are configured as 0 Hz fixed frequency 38 #clock-cells = <0>; 39 clock-frequency = <0>; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 48 #clock-cells = <0>; 49 clock-frequency = <0>; 55 #clock-cells = <0>; 57 clock-frequency = <0>; 62 #size-cells = <0>; [all …]
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H A D | r8a7791.dtsi | 40 * The external audio clocks are configured as 0 Hz fixed frequency 46 #clock-cells = <0>; 47 clock-frequency = <0>; 51 #clock-cells = <0>; 52 clock-frequency = <0>; 56 #clock-cells = <0>; 57 clock-frequency = <0>; 63 #clock-cells = <0>; 65 clock-frequency = <0>; 70 #size-cells = <0>; [all …]
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H A D | r8a7790.dtsi | 41 * The external audio clocks are configured as 0 Hz fixed frequency 47 #clock-cells = <0>; 48 clock-frequency = <0>; 52 #clock-cells = <0>; 53 clock-frequency = <0>; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 64 #clock-cells = <0>; 66 clock-frequency = <0>; 71 #size-cells = <0>; [all …]
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/openbmc/linux/arch/arm/boot/dts/renesas/ |
H A D | r8a7792.dtsi | 40 #clock-cells = <0>; 42 clock-frequency = <0>; 47 #size-cells = <0>; 49 cpu0: cpu@0 { 52 reg = <0>; 71 L2_CA15: cache-controller-0 { 82 #clock-cells = <0>; 84 clock-frequency = <0>; 97 #clock-cells = <0>; 99 clock-frequency = <0>; [all …]
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H A D | r8a77470.dtsi | 27 #size-cells = <0>; 29 cpu0: cpu@0 { 32 reg = <0>; 51 L2_CA7: cache-controller-0 { 62 #clock-cells = <0>; 64 clock-frequency = <0>; 77 #clock-cells = <0>; 79 clock-frequency = <0>; 93 reg = <0 0xe6020000 0 0x0c>; 104 reg = <0 0xe6050000 0 0x50>; [all …]
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H A D | r8a7794.dtsi | 34 * The external audio clocks are configured as 0 Hz fixed frequency 40 #clock-cells = <0>; 41 clock-frequency = <0>; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 50 #clock-cells = <0>; 51 clock-frequency = <0>; 57 #clock-cells = <0>; 59 clock-frequency = <0>; 64 #size-cells = <0>; [all …]
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H A D | r8a7793.dtsi | 32 * The external audio clocks are configured as 0 Hz fixed frequency 38 #clock-cells = <0>; 39 clock-frequency = <0>; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 48 #clock-cells = <0>; 49 clock-frequency = <0>; 55 #clock-cells = <0>; 57 clock-frequency = <0>; 62 #size-cells = <0>; [all …]
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H A D | r8a7745.dtsi | 36 * The external audio clocks are configured as 0 Hz fixed 42 #clock-cells = <0>; 43 clock-frequency = <0>; 47 #clock-cells = <0>; 48 clock-frequency = <0>; 52 #clock-cells = <0>; 53 clock-frequency = <0>; 59 #clock-cells = <0>; 61 clock-frequency = <0>; 66 #size-cells = <0>; [all …]
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H A D | r8a7742.dtsi | 19 * The external audio clocks are configured as 0 Hz fixed frequency 25 #clock-cells = <0>; 26 clock-frequency = <0>; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 35 #clock-cells = <0>; 36 clock-frequency = <0>; 42 #clock-cells = <0>; 44 clock-frequency = <0>; 49 #size-cells = <0>; [all …]
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H A D | r8a7791.dtsi | 40 * The external audio clocks are configured as 0 Hz fixed frequency 46 #clock-cells = <0>; 47 clock-frequency = <0>; 51 #clock-cells = <0>; 52 clock-frequency = <0>; 56 #clock-cells = <0>; 57 clock-frequency = <0>; 63 #clock-cells = <0>; 65 clock-frequency = <0>; 70 #size-cells = <0>; [all …]
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H A D | r8a7743.dtsi | 19 * The external audio clocks are configured as 0 Hz fixed frequency 25 #clock-cells = <0>; 26 clock-frequency = <0>; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 37 #clock-cells = <0>; 38 clock-frequency = <0>; 44 #clock-cells = <0>; 46 clock-frequency = <0>; 51 #size-cells = <0>; [all …]
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H A D | r8a7744.dtsi | 19 * The external audio clocks are configured as 0 Hz fixed frequency 25 #clock-cells = <0>; 26 clock-frequency = <0>; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 37 #clock-cells = <0>; 38 clock-frequency = <0>; 44 #clock-cells = <0>; 46 clock-frequency = <0>; 51 #size-cells = <0>; [all …]
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H A D | r8a7790.dtsi | 41 * The external audio clocks are configured as 0 Hz fixed frequency 47 #clock-cells = <0>; 48 clock-frequency = <0>; 52 #clock-cells = <0>; 53 clock-frequency = <0>; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 64 #clock-cells = <0>; 66 clock-frequency = <0>; 71 #size-cells = <0>; [all …]
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