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/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dcpu.h12 #define S5PC1XX_ADDR_BASE 0xE0000000
15 #define S5PC100_PRO_ID 0xE0000000
16 #define S5PC100_CLOCK_BASE 0xE0100000
17 #define S5PC100_GPIO_BASE 0xE0300000
18 #define S5PC100_VIC0_BASE 0xE4000000
19 #define S5PC100_VIC1_BASE 0xE4100000
20 #define S5PC100_VIC2_BASE 0xE4200000
21 #define S5PC100_DMC_BASE 0xE6000000
22 #define S5PC100_SROMC_BASE 0xE7000000
23 #define S5PC100_ONENAND_BASE 0xE7100000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Damd-ccp.txt14 reg = <0 0xe0100000 0 0x10000>;
16 interrupts = <0 3 4>;
/openbmc/u-boot/arch/nds32/include/asm/arch-ae3xx/
H A Dae3xx.h14 #define CONFIG_FTSMC020_BASE 0xe0400000
16 #define CONFIG_FTDMAC020_BASE 0xf0c00000
18 #define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000
20 #define CONFIG_RESERVED_01_BASE 0xe0500000
22 #define CONFIG_RESERVED_02_BASE 0xf0800000
24 #define CONFIG_RESERVED_03_BASE 0xf0900000
26 #define CONFIG_FTMAC100_BASE 0xe0100000
28 #define CONFIG_RESERVED_04_BASE 0xf1000000
33 #define CONFIG_FTUART010_01_BASE 0xf0200000
35 #define CONFIG_FTUART010_02_BASE 0xf0300000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,s5pv210-clock.yaml59 xxti: clock-0 {
61 clock-frequency = <0>;
63 #clock-cells = <0>;
68 clock-frequency = <0>;
70 #clock-cells = <0>;
75 reg = <0xe0100000 0x10000>;
/openbmc/linux/arch/arm/mach-spear/
H A Dspear.h18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
/openbmc/u-boot/arch/nds32/dts/
H A Dae3xx.dts15 …/* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug mem…
16 bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
21 memory@0 {
23 reg = <0x00000000 0x40000000>;
27 #clock-cells = <0>;
34 #size-cells = <0>;
35 cpu@0 {
37 reg = <0>;
51 reg = <0xf0300000 0x1000>;
61 reg = <0xf0400000 0x1000>;
[all …]
/openbmc/qemu/tests/qtest/libqos/
H A Darm-xilinx-zynq-a9-machine.c35 #define XILINX_ZYNQ_A9_RAM_ADDR 0
36 #define XILINX_ZYNQ_A9_RAM_SIZE 0x20000000
70 alloc_init(&machine->alloc, 0, in qos_create_machine_arm_xilinx_zynq_a9()
79 qos_init_sdhci_mm(&machine->sdhci, qts, 0xe0100000, &(QSDHCIProperties) { in qos_create_machine_arm_xilinx_zynq_a9()
81 .baseclock = 0, in qos_create_machine_arm_xilinx_zynq_a9()
83 .capab.reg = 0x69ec0080, in qos_create_machine_arm_xilinx_zynq_a9()
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-mmio.yaml40 of GPIOs is set by the width, with bit 0 corresponding to GPIO 0.
54 actively writing the line with 0.
95 reg = <0x1f300010 0x4>;
104 reg = <0xe0100000 0x1>;
113 reg = <0xfffe0406 2>, <0xfffe040a 2>;
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc832x_rdb.dts26 #size-cells = <0>;
28 PowerPC,8323@0 {
30 reg = <0x0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
43 reg = <0x00000000 0x04000000>;
51 ranges = <0x0 0xe0000000 0x00100000>;
[all …]
H A Dac14xx.dts25 PowerPC,5121@0 {
33 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
41 ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */
42 0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */
43 0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */
44 0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */
45 0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */
46 0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */
48 flash@0,0 {
50 reg = <0 0x00000000 0x04000000>;
[all …]
H A Dsequoia.dts22 dcr-parent = <&{/cpus/cpu@0}>;
35 #size-cells = <0>;
37 cpu@0 {
40 reg = <0x00000000>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
54 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
60 cell-index = <0>;
61 dcr-reg = <0x0c0 0x009>;
62 #address-cells = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-pl022.yaml47 runtime power management system suspends the device. A setting of 0
78 "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
87 - 0 # SPI
95 - 0 # interrupt mode
103 minimum: 0
109 minimum: 0
115 minimum: 0x03
116 maximum: 0x1f
121 enum: [0, 1]
126 enum: [0, 1]
[all …]
/openbmc/u-boot/board/samsung/smdkc100/
H A Dlowlevel_init.S23 mov r5, #0
28 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
29 orr r0, r0, #0x0
34 ldr r1, =0x9
38 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
39 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
40 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
43 mvn r3, #0x0
44 str r3, [r0, #0x14] @INTENCLEAR
45 str r3, [r1, #0x14] @INTENCLEAR
[all …]
/openbmc/u-boot/board/samsung/goni/
H A Dlowlevel_init.S18 * r7 has S5PC100 GPIO base, 0xE0300000
19 * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
28 mov r5, #0
35 mov r1, #0x00010000
47 and r1, r1, #0x000D0000
48 cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
53 addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
54 addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
55 ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
56 bic r1, r1, #(0xf << 4) @ 1 * 4-bit
[all …]
/openbmc/u-boot/arch/riscv/dts/
H A Dae350_64.dts21 #size-cells = <0>;
23 CPU0: cpu@0 {
25 reg = <0>;
31 d-cache-size = <0x8000>;
41 memory@0 {
43 reg = <0x0 0x00000000 0x0 0x40000000>;
57 reg = <0x0 0xe4000000 0x0 0x2000000>;
67 reg = <0x0 0xe6400000 0x0 0x400000>;
75 reg = <0x0 0xe6000000 0x0 0x100000>;
80 #clock-cells = <0>;
[all …]
H A Dae350_32.dts21 #size-cells = <0>;
23 CPU0: cpu@0 {
25 reg = <0>;
31 d-cache-size = <0x8000>;
41 memory@0 {
43 reg = <0x00000000 0x40000000>;
57 reg = <0xe4000000 0x2000000>;
67 reg = <0xe6400000 0x400000>;
75 reg = <0xe6000000 0x100000>;
80 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear13xx.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
36 reg = < 0xec801000 0x1000 >,
37 < 0xec800100 0x0100 >;
42 interrupts = <0 6 0x04>,
43 <0 7 0x04>;
48 reg = <0xed000000 0x1000>;
56 reg = <0 0x40000000>;
79 ranges = <0x50000000 0x50000000 0x10000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml137 enum: [0, 1]
158 enum: [0, 1, 2]
159 default: 0
185 reg = <0xe0100000 0x1000>;
189 interrupts = <0 24 4>;
195 reg = <0xe2800000 0x1000>;
199 interrupts = <0 24 4>;
210 reg = <0xfe330000 0x10000>;
220 #clock-cells = <0>;
227 interrupts = <0 48 4>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-soc.dtsi20 reg = <0x0 0xe1110000 0 0x1000>,
21 <0x0 0xe112f000 0 0x2000>,
22 <0x0 0xe1140000 0 0x2000>,
23 <0x0 0xe1160000 0 0x2000>;
24 interrupts = <1 9 0xf04>;
25 ranges = <0 0 0 0xe1100000 0 0x100000>;
29 reg = <0x0 0x00080000 0 0x1000>;
35 interrupts = <1 13 0xff04>,
36 <1 14 0xff04>,
37 <1 11 0xff04>,
[all …]
/openbmc/u-boot/include/configs/
H A Deb_cpu5282.h18 #define CONFIG_SYS_UART_PORT (0)
34 #define STATUS_LED_ACTIVE 0
41 #define CONFIG_ENV_ADDR 0xFF040000
42 #define CONFIG_ENV_SECT_SIZE 0x00020000
58 #define CONFIG_SYS_LOAD_ADDR 0x20000
60 #define CONFIG_SYS_MEMTEST_START 0x100000
61 #define CONFIG_SYS_MEMTEST_END 0x400000
72 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
73 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
85 #define CONFIG_SYS_FEC0_PINMUX 0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
50 interrupts = <0 5 4>, <0 6 4>;
52 reg = <0xf8891000 0x1000>,
53 <0xf8893000 0x1000>;
75 reg = <0xf8007100 0x20>;
76 interrupts = <0 7 4>;
86 reg = <0xe0008000 0x1000>;
87 interrupts = <0 28 4>;
[all …]
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
[all …]
/openbmc/qemu/hw/arm/
H A Dxilinx_zynq.c59 #define MPCORE_PERIPHBASE 0xF8F00000
60 #define ZYNQ_BOARD_MIDR 0x413FC090
66 #define BOARD_SETUP_ADDR 0x100
68 #define SLCR_LOCK_OFFSET 0x004
69 #define SLCR_UNLOCK_OFFSET 0x008
70 #define SLCR_ARM_PLL_OFFSET 0x100
72 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d
73 #define SLCR_XILINX_LOCK_KEY 0x767b
75 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
77 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
[all …]
H A Dmps3r.c83 #define PERIPHBASE 0xf0000000
136 .base = 0x00000000,
137 .size = 0x00008000,
138 .mrindex = 0,
142 .base = 0x08000000,
143 .size = 0x00800000,
148 .base = 0x10000000,
149 .size = 0x00080000,
153 .base = 0x20000000,
158 .base = 0xee000000,
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210.dtsi46 #size-cells = <0>;
48 cpu@0 {
51 reg = <0>;
55 xxti: oscillator-0 {
57 clock-frequency = <0>;
59 #clock-cells = <0>;
64 clock-frequency = <0>;
66 #clock-cells = <0>;
77 reg = <0xb0600000 0x2000>,
78 <0xb0000000 0x20000>,
[all …]