1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2b841b6e9Srick /* 3b841b6e9Srick * Copyright (C) 2016 Andes Technology Corporation 4b841b6e9Srick * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com> 5b841b6e9Srick * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 6b841b6e9Srick */ 7b841b6e9Srick 8b841b6e9Srick #ifndef __AE3XX_H 9b841b6e9Srick #define __AE3XX_H 10b841b6e9Srick 11b841b6e9Srick /* Hardware register bases */ 12b841b6e9Srick 13b841b6e9Srick /* Static Memory Controller (SRAM) */ 14b841b6e9Srick #define CONFIG_FTSMC020_BASE 0xe0400000 15b841b6e9Srick /* DMA Controller */ 16b841b6e9Srick #define CONFIG_FTDMAC020_BASE 0xf0c00000 17b841b6e9Srick /* AHB-to-APB Bridge */ 18b841b6e9Srick #define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000 19b841b6e9Srick /* Reserved */ 20b841b6e9Srick #define CONFIG_RESERVED_01_BASE 0xe0500000 21b841b6e9Srick /* Reserved */ 22b841b6e9Srick #define CONFIG_RESERVED_02_BASE 0xf0800000 23b841b6e9Srick /* Reserved */ 24b841b6e9Srick #define CONFIG_RESERVED_03_BASE 0xf0900000 25b841b6e9Srick /* Ethernet */ 26b841b6e9Srick #define CONFIG_FTMAC100_BASE 0xe0100000 27b841b6e9Srick /* Reserved */ 28b841b6e9Srick #define CONFIG_RESERVED_04_BASE 0xf1000000 29b841b6e9Srick 30b841b6e9Srick /* APB Device definitions */ 31b841b6e9Srick 32b841b6e9Srick /* UART1 */ 33b841b6e9Srick #define CONFIG_FTUART010_01_BASE 0xf0200000 34b841b6e9Srick /* UART2 */ 35b841b6e9Srick #define CONFIG_FTUART010_02_BASE 0xf0300000 36b841b6e9Srick /* Counter/Timers */ 37b841b6e9Srick #define CONFIG_FTTMR010_BASE 0xf0400000 38b841b6e9Srick /* Watchdog Timer */ 39b841b6e9Srick #define CONFIG_FTWDT010_BASE 0xf0500000 40b841b6e9Srick /* Real Time Clock */ 41b841b6e9Srick #define CONFIG_FTRTC010_BASE 0xf0600000 42b841b6e9Srick /* GPIO */ 43b841b6e9Srick #define CONFIG_FTGPIO010_BASE 0xf0700000 44b841b6e9Srick /* I2C */ 45b841b6e9Srick #define CONFIG_FTIIC010_BASE 0xf0a00000 46b841b6e9Srick 47b841b6e9Srick /* The following address was not defined in Linux */ 48b841b6e9Srick 49b841b6e9Srick /* Synchronous Serial Port Controller (SSP) 01 */ 50b841b6e9Srick #define CONFIG_FTSSP010_01_BASE 0xf0d00000 51b841b6e9Srick #endif /* __AE3XX_H */ 52