Searched +full:0 +full:xd0400000 (Results 1 – 5 of 5) sorted by relevance
12 #define CONFIG_SYS_FLASH_BASE 0x0800000013 #define CONFIG_SYS_INIT_SP_ADDR 0x2404000018 #define CONFIG_SYS_LOAD_ADDR 0xD040000019 #define CONFIG_LOADADDR 0xD040000034 func(MMC, mmc, 0)38 "kernel_addr_r=0xD0008000\0" \39 "fdtfile=stm32h743i-eval.dtb\0" \40 "fdt_addr_r=0xD0700000\0" \41 "scriptaddr=0xD0800000\0" \42 "pxefile_addr_r=0xD0800000\0" \[all …]
12 #define CONFIG_SYS_FLASH_BASE 0x0800000013 #define CONFIG_SYS_INIT_SP_ADDR 0x2404000018 #define CONFIG_SYS_LOAD_ADDR 0xD040000019 #define CONFIG_LOADADDR 0xD040000034 func(MMC, mmc, 0)38 "kernel_addr_r=0xD0008000\0" \39 "fdtfile=stm32h743i-disco.dtb\0" \40 "fdt_addr_r=0xD0700000\0" \41 "scriptaddr=0xD0800000\0" \42 "pxefile_addr_r=0xD0800000\0" \[all …]
55 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region62 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of72 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can83 normally mapped to the 0x0 address of this region, while eDMA84 is available at 0x80000 base address.149 pattern: '^dma([0-9]|1[0-5])?$'222 reg = <0xdfc00000 0x0001000>, /* IP registers */223 <0xd0000000 0x0002000>; /* Configuration space */227 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,228 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;[all …]
27 // base address: 0x028 …BIF_BX_PF_MM_INDEX 0x000029 …ne mmBIF_BX_PF_MM_INDEX_BASE_IDX 030 …BIF_BX_PF_MM_DATA 0x000131 …ne mmBIF_BX_PF_MM_DATA_BASE_IDX 032 …BIF_BX_PF_MM_INDEX_HI 0x000633 …ne mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX 037 // base address: 0x038 …SYSHUB_INDEX_OVLP 0x000839 …ne mmSYSHUB_INDEX_OVLP_BASE_IDX 0[all …]
29 // base address: 0x030 …BIF_BX0_PCIE_INDEX 0x000c31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 032 …BIF_BX0_PCIE_DATA 0x000d33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 034 …BIF_BX0_PCIE_INDEX2 0x000e35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 036 …BIF_BX0_PCIE_DATA2 0x000f37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 038 …BIF_BX0_PCIE_INDEX_HI 0x0010[all …]