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/openbmc/linux/arch/sh/kernel/cpu/sh3/
H A Dsetup-sh7720.c26 [0] = {
27 .start = 0xa413fec0,
28 .end = 0xa413fec0 + 0x28 - 1,
33 .start = evt2irq(0x480),
59 DEFINE_RES_MEM(0xa4430000, 0x100),
60 DEFINE_RES_IRQ(evt2irq(0xc00)),
65 .id = 0,
80 DEFINE_RES_MEM(0xa4438000, 0x100),
81 DEFINE_RES_IRQ(evt2irq(0xc20)),
95 [0] = {
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3288-vyasa-u-boot.dtsi7 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
8 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
9 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
10 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
11 0x5 0x0>;
12 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
13 0xa60 0x40 0x10 0x0>;
15 rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
H A Drk3288-miqi.dts19 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
20 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
21 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
22 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
23 0x5 0x0>;
24 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
25 0xa60 0x40 0x10 0x0>;
26 rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
H A Drk3288-popmetal.dts19 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
20 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
21 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
22 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
23 0x5 0x0>;
24 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
25 0xa60 0x40 0x10 0x0>;
26 rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
H A Drk3288-firefly.dts24 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
25 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
26 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
27 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
28 0x5 0x0>;
29 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
30 0xa60 0x40 0x10 0x0>;
32 rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
36 gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
49 rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
[all …]
H A Drk3288-veyron-jerry.dts28 pinctrl-0 = <&lcd_enable_h>;
38 pinctrl-0 = <&avdd_1v8_disp_en>;
50 pinctrl-0 = <&bl_pwr_en>;
60 sound-dai = <&i2s 0>;
64 sound-dai = <&max98090 0>;
70 rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
71 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
72 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
73 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
74 0x5 0x0>;
[all …]
H A Drk3288-rock2-square.dts56 pinctrl-0 = <&ir_int>;
70 #sound-dai-cells = <0>;
78 pinctrl-0 = <&host_vbus_drv>;
90 pinctrl-0 = <&sdmmc_pwr>;
107 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
125 reg = <0x51>;
126 #clock-cells = <0>;
132 pinctrl-0 = <&pmic_int>;
151 rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
157 rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
[all …]
H A Drk3288-phycore-rdk.dts66 pinctrl-0 = <&user_button_pins>;
68 button@0 {
71 gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
87 pinctrl-0 = <&host0_vbus_drv>;
97 gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
99 pinctrl-0 = <&host1_vbus_drv>;
111 pinctrl-0 = <&otg_vbus_drv>;
122 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
123 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
124 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
[all …]
/openbmc/linux/arch/sh/drivers/pci/
H A Dfixups-sdk7780.c16 #define IRQ_INTA evt2irq(0xa20)
17 #define IRQ_INTB evt2irq(0xa40)
18 #define IRQ_INTC evt2irq(0xa60)
19 #define IRQ_INTD evt2irq(0xa80)
/openbmc/linux/arch/sh/include/mach-se/mach/
H A Dse7780.h17 #define PA_ROM 0xa0000000 /* EPROM */
18 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
19 #define PA_FROM 0xa1000000 /* Flash-ROM */
20 #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
21 #define PA_EXT1 0xa4000000
22 #define PA_EXT1_SIZE 0x04000000
25 #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
26 #define PA_SDRAM_SIZE 0x08000000
28 #define PA_EXT4 0xb0000000
29 #define PA_EXT4_SIZE 0x04000000
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A Dodm_RegDefine11N.h13 #define ODM_REG_RF_MODE_11N 0x00
14 #define ODM_REG_RF_0B_11N 0x0B
15 #define ODM_REG_CHNBW_11N 0x18
16 #define ODM_REG_T_METER_11N 0x24
17 #define ODM_REG_RF_25_11N 0x25
18 #define ODM_REG_RF_26_11N 0x26
19 #define ODM_REG_RF_27_11N 0x27
20 #define ODM_REG_RF_2B_11N 0x2B
21 #define ODM_REG_RF_2C_11N 0x2C
22 #define ODM_REG_RXRF_A3_11N 0x3C
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-scc-qmc.yaml60 const: 0
63 '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
70 minimum: 0
125 reg = <0xa60 0x20>,
126 <0x3f00 0xc0>,
127 <0x2000 0x1000>;
133 #size-cells = <0>;
142 fsl,tx-ts-mask = <0x00000000 0x000000aa>;
143 fsl,rx-ts-mask = <0x00000000 0x000000aa>;
151 fsl,tx-ts-mask = <0x00000000 0x00000055>;
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Ddm.h11 #define MF_USC_LSC 0
14 #define MAIN_ANT 0
17 #define AUX_ANT_CG_TRX 0
18 #define MAIN_ANT_CGCS_RX 0
22 #define DM_REG_RF_MODE_11N 0x00
23 #define DM_REG_RF_0B_11N 0x0B
24 #define DM_REG_CHNBW_11N 0x18
25 #define DM_REG_T_METER_11N 0x24
26 #define DM_REG_RF_25_11N 0x25
27 #define DM_REG_RF_26_11N 0x26
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
15 #define DM_REG_RF_MODE_11N 0x00
16 #define DM_REG_RF_0B_11N 0x0B
17 #define DM_REG_CHNBW_11N 0x18
18 #define DM_REG_T_METER_11N 0x24
19 #define DM_REG_RF_25_11N 0x25
20 #define DM_REG_RF_26_11N 0x26
21 #define DM_REG_RF_27_11N 0x27
[all …]
/openbmc/linux/Documentation/devicetree/bindings/scsi/
H A Dhisilicon-sas.txt67 sas-addr = [50 01 88 20 16 00 00 0a];
68 reg = <0x0 0xc1000000 0x0 0x10000>;
70 ctrl-reset-reg = <0xa60>;
71 ctrl-reset-sts-reg = <0x5a30>;
72 ctrl-clock-ena-reg = <0x338>;
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam437x-sbc-t43.dts21 AM4372_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
22 AM4372_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
23 AM4372_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
24 AM4372_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
25 AM4372_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
26 AM4372_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
27 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
28 AM4372_IOPAD(0x964, PIN_INPUT | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0_7 */
34 AM4372_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam0 hd -> DSS DATA 23 */
35 AM4372_IOPAD(0x9b4, PIN_OUTPUT_PULLUP | MUX_MODE2)
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt13 pclk_ddrupctl0: support clock for access protocol controller registers of channel 0
14 pclk_publ0: support clock for access phy controller registers of channel 0
25 …t * 32 * n_clk cycles.The automatic self refresh function is disabled when auto-self-refresh-cnt=0.
26 …wer-down-cnt n_clk cycles.The automatic power down function is disabled when auto-power-down-cnt=0.
28 0.DDR3_800D (5-5-5)
110 odt - 1 to enable DDR ODT, 0 to disable
120 reg = <0xff610000 0x3fc
121 0xff620000 0x294
122 0xff630000 0x3fc
123 0xff640000 0x294>;
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7770.c22 DEFINE_RES_MEM(0xff923000, 0x100),
23 DEFINE_RES_IRQ(evt2irq(0x9a0)),
28 .id = 0,
42 DEFINE_RES_MEM(0xff924000, 0x100),
43 DEFINE_RES_IRQ(evt2irq(0x9c0)),
62 DEFINE_RES_MEM(0xff925000, 0x100),
63 DEFINE_RES_IRQ(evt2irq(0x9e0)),
82 DEFINE_RES_MEM(0xff926000, 0x100),
83 DEFINE_RES_IRQ(evt2irq(0xa00)),
102 DEFINE_RES_MEM(0xff927000, 0x100),
[all …]
H A Dsetup-shx3.c20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
34 DEFINE_RES_MEM(0xffc30000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0x700)),
36 DEFINE_RES_IRQ(evt2irq(0x720)),
37 DEFINE_RES_IRQ(evt2irq(0x760)),
38 DEFINE_RES_IRQ(evt2irq(0x740)),
43 .id = 0,
57 DEFINE_RES_MEM(0xffc40000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x780)),
59 DEFINE_RES_IRQ(evt2irq(0x7a0)),
[all …]
H A Dsetup-sh7763.c26 DEFINE_RES_MEM(0xffe00000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0x700)),
32 .id = 0,
47 DEFINE_RES_MEM(0xffe08000, 0x100),
48 DEFINE_RES_IRQ(evt2irq(0xb80)),
68 DEFINE_RES_MEM(0xffe10000, 0x100),
69 DEFINE_RES_IRQ(evt2irq(0xf00)),
83 [0] = {
84 .start = 0xffe80000,
85 .end = 0xffe80000 + 0x58 - 1,
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh7750.c19 [0] = {
20 .start = 0xffc80000,
21 .end = 0xffc80000 + 0x58 - 1,
26 .start = evt2irq(0x480),
43 DEFINE_RES_MEM(0xffe00000, 0x20),
44 DEFINE_RES_IRQ(evt2irq(0x4e0)),
49 .id = 0,
63 DEFINE_RES_MEM(0xffe80000, 0x100),
64 DEFINE_RES_IRQ(evt2irq(0x700)),
82 DEFINE_RES_MEM(0xffd80000, 0x30),
[all …]
/openbmc/linux/drivers/net/ethernet/ti/icssg/
H A Dicssg_classifier.c22 #define FT1_SLOT_SIZE 0x10 /* bytes */
25 #define FT1_DA0 0x0
26 #define FT1_DA1 0x4
27 #define FT1_DA0_MASK 0x8
28 #define FT1_DA1_MASK 0xc
36 #define FT1_START_MASK GENMASK(14, 0)
42 FT1_CFG_TYPE_DISABLED = 0,
49 #define FT1_CFG_MASK(n) (0x3 << FT1_CFG_SHIFT((n)))
53 #define FT3_SLOT_SIZE 0x20 /* bytes */
56 #define FT3_START 0
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun50i_h6.h13 u32 pll1_cfg; /* 0x000 pll1 (cpux) control */
15 u32 pll5_cfg; /* 0x010 pll5 (ddr) control */
17 u32 pll6_cfg; /* 0x020 pll6 (periph0) control */
19 u32 pll_periph1_cfg; /* 0x028 pll periph1 control */
21 u32 pll7_cfg; /* 0x030 pll7 (gpu) control */
23 u32 pll3_cfg; /* 0x040 pll3 (video0) control */
25 u32 pll_video1_cfg; /* 0x048 pll video1 control */
27 u32 pll4_cfg; /* 0x058 pll4 (ve) control */
29 u32 pll10_cfg; /* 0x060 pll10 (de) control */
31 u32 pll9_cfg; /* 0x070 pll9 (hsic) control */
[all …]

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