| /openbmc/linux/drivers/mfd/ |
| H A D | wm8350-regmap.c | 23 { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Reset/ID */
24 { 0x7CFF, 0x0C00, 0x0000 }, /* R1 - ID */
25 { 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */
26 { 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */
27 { 0xFEF7, 0xFEF7, 0xF800 }, /* R4 - System Control 2 */
28 { 0x80FF, 0x80FF, 0x8000 }, /* R5 - System Hibernate */
29 { 0xFB0E, 0xFB0E, 0x0000 }, /* R6 - Interface Control */
30 { 0x0000, 0x0000, 0x0000 }, /* R7 */
31 { 0xE537, 0xE537, 0xFFFF }, /* R8 - Power mgmt (1) */
32 { 0x0FF3, 0x0FF3, 0xFFFF }, /* R9 - Power mgmt (2) */
[all …]
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| /openbmc/linux/drivers/infiniband/hw/ocrdma/ |
| H A D | ocrdma_sli.h | 47 OCRDMA_ASIC_GEN_SKH_R = 0x04,
48 OCRDMA_ASIC_GEN_LANCER = 0x0B
52 OCRDMA_ASIC_REV_A0 = 0x00,
53 OCRDMA_ASIC_REV_B0 = 0x10,
54 OCRDMA_ASIC_REV_C0 = 0x20
129 OCRDMA_DB_RQ_OFFSET = 0xE0,
130 OCRDMA_DB_GEN2_RQ_OFFSET = 0x100,
131 OCRDMA_DB_SQ_OFFSET = 0x60,
132 OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0,
135 OCRDMA_DB_CQ_OFFSET = 0x120,
[all …]
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| /openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/ |
| H A D | npc_profile.h | 11 #define NPC_KPU_PROFILE_VER 0x0000000100070000
12 #define NPC_KPU_VER_MAJ(ver) ((u16)(((ver) >> 32) & 0xFFFF))
13 #define NPC_KPU_VER_MIN(ver) ((u16)(((ver) >> 16) & 0xFFFF))
14 #define NPC_KPU_VER_PATCH(ver) ((u16)((ver) & 0xFFFF))
16 #define NPC_IH_W 0x8000
17 #define NPC_IH_UTAG 0x2000
19 #define NPC_ETYPE_IP 0x0800
20 #define NPC_ETYPE_IP6 0x86dd
21 #define NPC_ETYPE_ARP 0x0806
22 #define NPC_ETYPE_RARP 0x8035
[all …]
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| /openbmc/linux/drivers/media/dvb-frontends/drx39xyj/ |
| H A D | drxj_map.h | 37 * Generated by: IDF:x 1.3.0
56 #define ATV_COMM_EXEC__A 0xC00000
58 #define ATV_COMM_EXEC__M 0x3
59 #define ATV_COMM_EXEC__PRE 0x0
60 #define ATV_COMM_EXEC_STOP 0x0
61 #define ATV_COMM_EXEC_ACTIVE 0x1
62 #define ATV_COMM_EXEC_HOLD 0x2
64 #define ATV_COMM_STATE__A 0xC00001
66 #define ATV_COMM_STATE__M 0xFFFF
67 #define ATV_COMM_STATE__PRE 0x0
[all …]
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | iwmmxt_helper.c | 30 #define SIMD8_SET(v, n, b) ((v != 0) << ((((b) + 1) * 4) + (n)))
31 #define SIMD16_SET(v, n, h) ((v != 0) << ((((h) + 1) * 8) + (n)))
32 #define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n)))
33 #define SIMD64_SET(v, n) ((v != 0) << (32 + (n)))
40 #define NBIT8(x) ((x) & 0x80)
41 #define NBIT16(x) ((x) & 0x8000)
42 #define NBIT32(x) ((x) & 0x80000000)
43 #define NBIT64(x) ((x) & 0x8000000000000000ULL)
44 #define ZBIT8(x) (((x) & 0xff) == 0)
45 #define ZBIT16(x) (((x) & 0xffff) == 0)
[all …]
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| /openbmc/linux/drivers/media/platform/verisilicon/ |
| H A D | rockchip_vpu981_regs.h | 28 #define av1_dec_e AV1_DEC_REG(1, 0, 0x1)
29 #define av1_dec_abort_e AV1_DEC_REG(1, 5, 0x1)
30 #define av1_dec_tile_int_e AV1_DEC_REG(1, 7, 0x1)
32 #define av1_dec_clk_gate_e AV1_DEC_REG(2, 10, 0x1)
34 #define av1_dec_out_ec_bypass AV1_DEC_REG(3, 8, 0x1)
35 #define av1_write_mvs_e AV1_DEC_REG(3, 12, 0x1)
36 #define av1_filtering_dis AV1_DEC_REG(3, 14, 0x1)
37 #define av1_dec_out_dis AV1_DEC_REG(3, 15, 0x1)
38 #define av1_dec_out_ec_byte_word AV1_DEC_REG(3, 16, 0x1)
39 #define av1_skip_mode AV1_DEC_REG(3, 26, 0x1)
[all …]
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| /openbmc/linux/drivers/comedi/drivers/ |
| H A D | ni_pcimio.c | 108 * 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
109 * be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
210 .ai_maxdata = 0xffff,
216 .ao_maxdata = 0x0fff,
224 .ai_maxdata = 0xffff,
230 .ao_maxdata = 0xffff,
239 .ai_maxdata = 0xffff,
245 .ao_maxdata = 0xffff,
253 .ai_maxdata = 0xffff,
259 .ao_maxdata = 0xffff,
[all …]
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| /openbmc/linux/drivers/gpu/drm/i915/gvt/ |
| H A D | mmio_context.c | 50 {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
51 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
52 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
53 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
54 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
55 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
56 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
57 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
58 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
59 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | brcm,iproc-sba.txt | 21 mboxes = <&raid_mbox 0 0x1 0xffff>,
22 <&raid_mbox 1 0x1 0xffff>,
23 <&raid_mbox 2 0x1 0xffff>,
24 <&raid_mbox 3 0x1 0xffff>,
25 <&raid_mbox 4 0x1 0xffff>,
26 <&raid_mbox 5 0x1 0xffff>,
27 <&raid_mbox 6 0x1 0xffff>,
28 <&raid_mbox 7 0x1 0xffff>;
|
| /openbmc/linux/drivers/usb/storage/ |
| H A D | unusual_datafab.h | 9 UNUSUAL_DEV( 0x07c4, 0xa000, 0x0000, 0x0015,
13 0),
17 * using the current driver...the 0xffff is arbitrary since I
20 * The 0xa003 and 0xa004 devices in particular I'm curious about.
26 UNUSUAL_DEV( 0x07c4, 0xa001, 0x0000, 0xffff,
30 0),
33 UNUSUAL_DEV( 0x07c4, 0xa002, 0x0000, 0xffff,
39 UNUSUAL_DEV( 0x07c4, 0xa003, 0x0000, 0xffff,
43 0),
45 UNUSUAL_DEV( 0x07c4, 0xa004, 0x0000, 0xffff,
[all …]
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| /openbmc/linux/drivers/gpu/drm/mxsfb/ |
| H A D | lcdif_regs.h | 15 #define LCDC_V8_CTRL 0x00
16 #define LCDC_V8_DISP_PARA 0x10
17 #define LCDC_V8_DISP_SIZE 0x14
18 #define LCDC_V8_HSYN_PARA 0x18
19 #define LCDC_V8_VSYN_PARA 0x1c
20 #define LCDC_V8_VSYN_HSYN_WIDTH 0x20
21 #define LCDC_V8_INT_STATUS_D0 0x24
22 #define LCDC_V8_INT_ENABLE_D0 0x28
23 #define LCDC_V8_INT_STATUS_D1 0x30
24 #define LCDC_V8_INT_ENABLE_D1 0x34
[all …]
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| /openbmc/linux/arch/m68k/ifpsp060/src/ |
| H A D | itest.S | 51 align 0x4
58 addq.l &0x4,%sp
63 addq.l &0x4,%sp
67 addq.l &0x4,%sp
74 movm.l &0x3f3c,-(%sp)
78 addq.l &0x4,%sp
84 addq.l &0x4,%sp
94 addq.l &0x4,%sp
104 addq.l &0x4,%sp
114 addq.l &0x4,%sp
[all …]
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| /openbmc/linux/drivers/staging/sm750fb/ |
| H A D | ddk750_reg.h | 6 #define DE_STATE1 0x100054
7 #define DE_STATE1_DE_ABORT BIT(0)
9 #define DE_STATE2 0x100058
14 #define SYSTEM_CTRL 0x000000
15 #define SYSTEM_CTRL_DPMS_MASK (0x3 << 30)
16 #define SYSTEM_CTRL_DPMS_VPHP (0x0 << 30)
17 #define SYSTEM_CTRL_DPMS_VPHN (0x1 << 30)
18 #define SYSTEM_CTRL_DPMS_VNHP (0x2 << 30)
19 #define SYSTEM_CTRL_DPMS_VNHN (0x3 << 30)
35 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_MASK (0x3 << 4)
[all …]
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| /openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/ |
| H A D | ael1002.c | 36 AEL100X_TX_CONFIG1 = 0xc002,
37 AEL1002_PWR_DOWN_HI = 0xc011,
38 AEL1002_PWR_DOWN_LO = 0xc012,
39 AEL1002_XFI_EQL = 0xc015,
40 AEL1002_LB_EN = 0xc017,
41 AEL_OPT_SETTINGS = 0xc017,
42 AEL_I2C_CTRL = 0xc30a,
43 AEL_I2C_DATA = 0xc30b,
44 AEL_I2C_STAT = 0xc30c,
45 AEL2005_GPIO_CTRL = 0xc214,
[all …]
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| /openbmc/linux/arch/sh/boards/mach-dreamcast/ |
| H A D | rtc.c | 7 * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org>
23 #define AICA_RTC_SECS_H 0xa0710000
24 #define AICA_RTC_SECS_L 0xa0710004
39 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
40 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
42 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
43 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
51 return 0; in aica_rtc_gettimeofday()
68 __raw_writel((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H); in aica_rtc_settimeofday()
69 __raw_writel((adj & 0xffff), AICA_RTC_SECS_L); in aica_rtc_settimeofday()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_sh_mask.h | 27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
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| /openbmc/linux/net/tipc/ |
| H A D | msg.h | 64 #define TIPC_CONN_MSG 0
146 #define TIPC_SKB_CB(__skb) ((struct tipc_skb_cb *)&((__skb)->cb[0]))
158 * --> Gap ACK blocks: <4, 5>, <11, 1>, <15, 4>, <20, 0>
173 * 31 16 15 0
230 * Word 0
234 return msg_bits(m, 0, 29, 7); in msg_version()
239 msg_set_bits(m, 0, 29, 7, TIPC_VERSION); in msg_set_version()
244 return msg_bits(m, 0, 25, 0xf); in msg_user()
254 msg_set_bits(m, 0, 25, 0xf, n); in msg_set_user()
259 return msg_bits(m, 0, 21, 0xf) << 2; in msg_hdr_sz()
[all …]
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| /openbmc/linux/drivers/net/ethernet/aquantia/atlantic/macsec/ |
| H A D | macsec_api.c | 23 } while (0); \
46 return (*data != 0xffff) ? 0 : -ETIME; in aq_mss_mdio_read()
52 return 0; in aq_mss_mdio_write()
82 for (i = 0; i < num_words; i += 2) { in set_raw_ingress_record()
96 0); in set_raw_ingress_record()
98 MSS_INGRESS_LUT_DATA_CTL_REGISTER_ADDR + i + 1, 0); in set_raw_ingress_record()
105 lut_op_reg.bits_0.lut_read = 0; in set_raw_ingress_record()
114 return 0; in set_raw_ingress_record()
135 lut_op_reg.bits_0.lut_write = 0; in get_raw_ingress_record()
148 memset(packed_record, 0, sizeof(u16) * num_words); in get_raw_ingress_record()
[all …]
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| /openbmc/linux/drivers/ssb/ |
| H A D | pci.c | 28 #define SSB_VERBOSE_PCICORESWITCH_DEBUG 0
35 int attempts = 0; in ssb_pci_switch_coreidx()
57 return 0; in ssb_pci_switch_coreidx()
91 return 0; in ssb_pci_xtal()
181 SPEX(_field[0], _offset + 0, _mask, _shift); \
189 } while (0)
196 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B, in ssb_crc8()
197 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21, in ssb_crc8()
198 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF, in ssb_crc8()
199 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5, in ssb_crc8()
[all …]
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| /openbmc/u-boot/net/ |
| H A D | checksum.c | 18 sum = 0; in compute_ip_checksum()
24 oddbyte = 0; in compute_ip_checksum()
25 ((u8 *)&oddbyte)[0] = *(u8 *)ptr; in compute_ip_checksum()
26 ((u8 *)&oddbyte)[1] = 0; in compute_ip_checksum()
29 sum = (sum >> 16) + (sum & 0xffff); in compute_ip_checksum()
31 sum = ~sum & 0xffff; in compute_ip_checksum()
40 sum = ~sum & 0xffff; in add_ip_checksums()
41 new = ~new & 0xffff; in add_ip_checksums()
47 new = ((new >> 8) & 0xff) | ((new << 8) & 0xff00); in add_ip_checksums()
50 if (checksum > 0xffff) in add_ip_checksums()
[all …]
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| /openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/ |
| H A D | dma_qm_0_masks.h | 23 #define DMA_QM_0_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define DMA_QM_0_GLBL_CFG0_PQF_EN_MASK 0x1
26 #define DMA_QM_0_GLBL_CFG0_CQF_EN_MASK 0x2
28 #define DMA_QM_0_GLBL_CFG0_CP_EN_MASK 0x4
30 #define DMA_QM_0_GLBL_CFG0_DMA_EN_MASK 0x8
33 #define DMA_QM_0_GLBL_CFG1_PQF_STOP_SHIFT 0
34 #define DMA_QM_0_GLBL_CFG1_PQF_STOP_MASK 0x1
36 #define DMA_QM_0_GLBL_CFG1_CQF_STOP_MASK 0x2
38 #define DMA_QM_0_GLBL_CFG1_CP_STOP_MASK 0x4
40 #define DMA_QM_0_GLBL_CFG1_DMA_STOP_MASK 0x8
[all …]
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| H A D | tpc0_qm_masks.h | 23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0x1
26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x2
28 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x4
30 #define TPC0_QM_GLBL_CFG0_DMA_EN_MASK 0x8
33 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
34 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0x1
36 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x2
38 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x4
40 #define TPC0_QM_GLBL_CFG1_DMA_STOP_MASK 0x8
[all …]
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| H A D | mme_qm_masks.h | 23 #define MME_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define MME_QM_GLBL_CFG0_PQF_EN_MASK 0x1
26 #define MME_QM_GLBL_CFG0_CQF_EN_MASK 0x2
28 #define MME_QM_GLBL_CFG0_CP_EN_MASK 0x4
30 #define MME_QM_GLBL_CFG0_DMA_EN_MASK 0x8
33 #define MME_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
34 #define MME_QM_GLBL_CFG1_PQF_STOP_MASK 0x1
36 #define MME_QM_GLBL_CFG1_CQF_STOP_MASK 0x2
38 #define MME_QM_GLBL_CFG1_CP_STOP_MASK 0x4
40 #define MME_QM_GLBL_CFG1_DMA_STOP_MASK 0x8
[all …]
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| /openbmc/linux/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop_reg.c | 84 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
85 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
86 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
87 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
91 .scale_yrgb_x = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 0x0),
92 .scale_yrgb_y = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 16),
100 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
101 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
102 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
103 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
[all …]
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| /openbmc/qemu/disas/ |
| H A D | m68k.c | 35 fields is contiguous. We number the bits with 0 being the most significant
67 /* Sign bit is always one bit long. 1 means negative, 0 means positive. */
74 very large number (e.g., given the exp_bias of 0x3fff and a 64
143 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
165 #define _m68k_undef 0
166 #define m68000 0x001
168 #define m68010 0x002
169 #define m68020 0x004
170 #define m68030 0x008
173 #define m68040 0x010
[all …]
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