1*727a4006SBenjamin Gaignard /* SPDX-License-Identifier: GPL-2.0-only */ 2*727a4006SBenjamin Gaignard /* 3*727a4006SBenjamin Gaignard * Copyright (c) 2022, Collabora 4*727a4006SBenjamin Gaignard * 5*727a4006SBenjamin Gaignard * Author: Benjamin Gaignard <benjamin.gaignard@collabora.com> 6*727a4006SBenjamin Gaignard */ 7*727a4006SBenjamin Gaignard 8*727a4006SBenjamin Gaignard #ifndef _ROCKCHIP_VPU981_REGS_H_ 9*727a4006SBenjamin Gaignard #define _ROCKCHIP_VPU981_REGS_H_ 10*727a4006SBenjamin Gaignard 11*727a4006SBenjamin Gaignard #include "hantro.h" 12*727a4006SBenjamin Gaignard 13*727a4006SBenjamin Gaignard #define AV1_SWREG(nr) ((nr) * 4) 14*727a4006SBenjamin Gaignard 15*727a4006SBenjamin Gaignard #define AV1_DEC_REG(b, s, m) \ 16*727a4006SBenjamin Gaignard ((const struct hantro_reg) { \ 17*727a4006SBenjamin Gaignard .base = AV1_SWREG(b), \ 18*727a4006SBenjamin Gaignard .shift = s, \ 19*727a4006SBenjamin Gaignard .mask = m, \ 20*727a4006SBenjamin Gaignard }) 21*727a4006SBenjamin Gaignard 22*727a4006SBenjamin Gaignard #define AV1_REG_INTERRUPT AV1_SWREG(1) 23*727a4006SBenjamin Gaignard #define AV1_REG_INTERRUPT_DEC_RDY_INT BIT(12) 24*727a4006SBenjamin Gaignard 25*727a4006SBenjamin Gaignard #define AV1_REG_CONFIG AV1_SWREG(2) 26*727a4006SBenjamin Gaignard #define AV1_REG_CONFIG_DEC_CLK_GATE_E BIT(10) 27*727a4006SBenjamin Gaignard 28*727a4006SBenjamin Gaignard #define av1_dec_e AV1_DEC_REG(1, 0, 0x1) 29*727a4006SBenjamin Gaignard #define av1_dec_abort_e AV1_DEC_REG(1, 5, 0x1) 30*727a4006SBenjamin Gaignard #define av1_dec_tile_int_e AV1_DEC_REG(1, 7, 0x1) 31*727a4006SBenjamin Gaignard 32*727a4006SBenjamin Gaignard #define av1_dec_clk_gate_e AV1_DEC_REG(2, 10, 0x1) 33*727a4006SBenjamin Gaignard 34*727a4006SBenjamin Gaignard #define av1_dec_out_ec_bypass AV1_DEC_REG(3, 8, 0x1) 35*727a4006SBenjamin Gaignard #define av1_write_mvs_e AV1_DEC_REG(3, 12, 0x1) 36*727a4006SBenjamin Gaignard #define av1_filtering_dis AV1_DEC_REG(3, 14, 0x1) 37*727a4006SBenjamin Gaignard #define av1_dec_out_dis AV1_DEC_REG(3, 15, 0x1) 38*727a4006SBenjamin Gaignard #define av1_dec_out_ec_byte_word AV1_DEC_REG(3, 16, 0x1) 39*727a4006SBenjamin Gaignard #define av1_skip_mode AV1_DEC_REG(3, 26, 0x1) 40*727a4006SBenjamin Gaignard #define av1_dec_mode AV1_DEC_REG(3, 27, 0x1f) 41*727a4006SBenjamin Gaignard 42*727a4006SBenjamin Gaignard #define av1_ref_frames AV1_DEC_REG(4, 0, 0xf) 43*727a4006SBenjamin Gaignard #define av1_pic_height_in_cbs AV1_DEC_REG(4, 6, 0x1fff) 44*727a4006SBenjamin Gaignard #define av1_pic_width_in_cbs AV1_DEC_REG(4, 19, 0x1fff) 45*727a4006SBenjamin Gaignard 46*727a4006SBenjamin Gaignard #define av1_ref_scaling_enable AV1_DEC_REG(5, 0, 0x1) 47*727a4006SBenjamin Gaignard #define av1_filt_level_base_gt32 AV1_DEC_REG(5, 1, 0x1) 48*727a4006SBenjamin Gaignard #define av1_error_resilient AV1_DEC_REG(5, 2, 0x1) 49*727a4006SBenjamin Gaignard #define av1_force_interger_mv AV1_DEC_REG(5, 3, 0x1) 50*727a4006SBenjamin Gaignard #define av1_allow_intrabc AV1_DEC_REG(5, 4, 0x1) 51*727a4006SBenjamin Gaignard #define av1_allow_screen_content_tools AV1_DEC_REG(5, 5, 0x1) 52*727a4006SBenjamin Gaignard #define av1_reduced_tx_set_used AV1_DEC_REG(5, 6, 0x1) 53*727a4006SBenjamin Gaignard #define av1_enable_dual_filter AV1_DEC_REG(5, 7, 0x1) 54*727a4006SBenjamin Gaignard #define av1_enable_jnt_comp AV1_DEC_REG(5, 8, 0x1) 55*727a4006SBenjamin Gaignard #define av1_allow_filter_intra AV1_DEC_REG(5, 9, 0x1) 56*727a4006SBenjamin Gaignard #define av1_enable_intra_edge_filter AV1_DEC_REG(5, 10, 0x1) 57*727a4006SBenjamin Gaignard #define av1_tempor_mvp_e AV1_DEC_REG(5, 11, 0x1) 58*727a4006SBenjamin Gaignard #define av1_allow_interintra AV1_DEC_REG(5, 12, 0x1) 59*727a4006SBenjamin Gaignard #define av1_allow_masked_compound AV1_DEC_REG(5, 13, 0x1) 60*727a4006SBenjamin Gaignard #define av1_enable_cdef AV1_DEC_REG(5, 14, 0x1) 61*727a4006SBenjamin Gaignard #define av1_switchable_motion_mode AV1_DEC_REG(5, 15, 0x1) 62*727a4006SBenjamin Gaignard #define av1_show_frame AV1_DEC_REG(5, 16, 0x1) 63*727a4006SBenjamin Gaignard #define av1_superres_is_scaled AV1_DEC_REG(5, 17, 0x1) 64*727a4006SBenjamin Gaignard #define av1_allow_warp AV1_DEC_REG(5, 18, 0x1) 65*727a4006SBenjamin Gaignard #define av1_disable_cdf_update AV1_DEC_REG(5, 19, 0x1) 66*727a4006SBenjamin Gaignard #define av1_preskip_segid AV1_DEC_REG(5, 20, 0x1) 67*727a4006SBenjamin Gaignard #define av1_delta_lf_present AV1_DEC_REG(5, 21, 0x1) 68*727a4006SBenjamin Gaignard #define av1_delta_lf_multi AV1_DEC_REG(5, 22, 0x1) 69*727a4006SBenjamin Gaignard #define av1_delta_lf_res_log AV1_DEC_REG(5, 23, 0x3) 70*727a4006SBenjamin Gaignard #define av1_strm_start_bit AV1_DEC_REG(5, 25, 0x7f) 71*727a4006SBenjamin Gaignard 72*727a4006SBenjamin Gaignard #define av1_stream_len AV1_DEC_REG(6, 0, 0xffffffff) 73*727a4006SBenjamin Gaignard 74*727a4006SBenjamin Gaignard #define av1_delta_q_present AV1_DEC_REG(7, 0, 0x1) 75*727a4006SBenjamin Gaignard #define av1_delta_q_res_log AV1_DEC_REG(7, 1, 0x3) 76*727a4006SBenjamin Gaignard #define av1_cdef_damping AV1_DEC_REG(7, 3, 0x3) 77*727a4006SBenjamin Gaignard #define av1_cdef_bits AV1_DEC_REG(7, 5, 0x3) 78*727a4006SBenjamin Gaignard #define av1_apply_grain AV1_DEC_REG(7, 7, 0x1) 79*727a4006SBenjamin Gaignard #define av1_num_y_points_b AV1_DEC_REG(7, 8, 0x1) 80*727a4006SBenjamin Gaignard #define av1_num_cb_points_b AV1_DEC_REG(7, 9, 0x1) 81*727a4006SBenjamin Gaignard #define av1_num_cr_points_b AV1_DEC_REG(7, 10, 0x1) 82*727a4006SBenjamin Gaignard #define av1_overlap_flag AV1_DEC_REG(7, 11, 0x1) 83*727a4006SBenjamin Gaignard #define av1_clip_to_restricted_range AV1_DEC_REG(7, 12, 0x1) 84*727a4006SBenjamin Gaignard #define av1_chroma_scaling_from_luma AV1_DEC_REG(7, 13, 0x1) 85*727a4006SBenjamin Gaignard #define av1_random_seed AV1_DEC_REG(7, 14, 0xffff) 86*727a4006SBenjamin Gaignard #define av1_blackwhite_e AV1_DEC_REG(7, 30, 0x1) 87*727a4006SBenjamin Gaignard 88*727a4006SBenjamin Gaignard #define av1_scaling_shift AV1_DEC_REG(8, 0, 0xf) 89*727a4006SBenjamin Gaignard #define av1_bit_depth_c_minus8 AV1_DEC_REG(8, 4, 0x3) 90*727a4006SBenjamin Gaignard #define av1_bit_depth_y_minus8 AV1_DEC_REG(8, 6, 0x3) 91*727a4006SBenjamin Gaignard #define av1_quant_base_qindex AV1_DEC_REG(8, 8, 0xff) 92*727a4006SBenjamin Gaignard #define av1_idr_pic_e AV1_DEC_REG(8, 16, 0x1) 93*727a4006SBenjamin Gaignard #define av1_superres_pic_width AV1_DEC_REG(8, 17, 0x7fff) 94*727a4006SBenjamin Gaignard 95*727a4006SBenjamin Gaignard #define av1_ref4_sign_bias AV1_DEC_REG(9, 2, 0x1) 96*727a4006SBenjamin Gaignard #define av1_ref5_sign_bias AV1_DEC_REG(9, 3, 0x1) 97*727a4006SBenjamin Gaignard #define av1_ref6_sign_bias AV1_DEC_REG(9, 4, 0x1) 98*727a4006SBenjamin Gaignard #define av1_mf1_type AV1_DEC_REG(9, 5, 0x7) 99*727a4006SBenjamin Gaignard #define av1_mf2_type AV1_DEC_REG(9, 8, 0x7) 100*727a4006SBenjamin Gaignard #define av1_mf3_type AV1_DEC_REG(9, 11, 0x7) 101*727a4006SBenjamin Gaignard #define av1_scale_denom_minus9 AV1_DEC_REG(9, 14, 0x7) 102*727a4006SBenjamin Gaignard #define av1_last_active_seg AV1_DEC_REG(9, 17, 0x7) 103*727a4006SBenjamin Gaignard #define av1_context_update_tile_id AV1_DEC_REG(9, 20, 0xfff) 104*727a4006SBenjamin Gaignard 105*727a4006SBenjamin Gaignard #define av1_tile_transpose AV1_DEC_REG(10, 0, 0x1) 106*727a4006SBenjamin Gaignard #define av1_tile_enable AV1_DEC_REG(10, 1, 0x1) 107*727a4006SBenjamin Gaignard #define av1_multicore_full_width AV1_DEC_REG(10, 2, 0xff) 108*727a4006SBenjamin Gaignard #define av1_num_tile_rows_8k AV1_DEC_REG(10, 10, 0x7f) 109*727a4006SBenjamin Gaignard #define av1_num_tile_cols_8k AV1_DEC_REG(10, 17, 0x7f) 110*727a4006SBenjamin Gaignard #define av1_multicore_tile_start_x AV1_DEC_REG(10, 24, 0xff) 111*727a4006SBenjamin Gaignard 112*727a4006SBenjamin Gaignard #define av1_use_temporal3_mvs AV1_DEC_REG(11, 0, 0x1) 113*727a4006SBenjamin Gaignard #define av1_use_temporal2_mvs AV1_DEC_REG(11, 1, 0x1) 114*727a4006SBenjamin Gaignard #define av1_use_temporal1_mvs AV1_DEC_REG(11, 2, 0x1) 115*727a4006SBenjamin Gaignard #define av1_use_temporal0_mvs AV1_DEC_REG(11, 3, 0x1) 116*727a4006SBenjamin Gaignard #define av1_comp_pred_mode AV1_DEC_REG(11, 4, 0x3) 117*727a4006SBenjamin Gaignard #define av1_high_prec_mv_e AV1_DEC_REG(11, 7, 0x1) 118*727a4006SBenjamin Gaignard #define av1_mcomp_filt_type AV1_DEC_REG(11, 8, 0x7) 119*727a4006SBenjamin Gaignard #define av1_multicore_expect_context_update AV1_DEC_REG(11, 11, 0x1) 120*727a4006SBenjamin Gaignard #define av1_multicore_sbx_offset AV1_DEC_REG(11, 12, 0x7f) 121*727a4006SBenjamin Gaignard #define av1_ulticore_tile_col AV1_DEC_REG(11, 19, 0x7f) 122*727a4006SBenjamin Gaignard #define av1_transform_mode AV1_DEC_REG(11, 27, 0x7) 123*727a4006SBenjamin Gaignard #define av1_dec_tile_size_mag AV1_DEC_REG(11, 30, 0x3) 124*727a4006SBenjamin Gaignard 125*727a4006SBenjamin Gaignard #define av1_seg_quant_sign AV1_DEC_REG(12, 2, 0xff) 126*727a4006SBenjamin Gaignard #define av1_max_cb_size AV1_DEC_REG(12, 10, 0x7) 127*727a4006SBenjamin Gaignard #define av1_min_cb_size AV1_DEC_REG(12, 13, 0x7) 128*727a4006SBenjamin Gaignard #define av1_comp_pred_fixed_ref AV1_DEC_REG(12, 16, 0x7) 129*727a4006SBenjamin Gaignard #define av1_multicore_tile_width AV1_DEC_REG(12, 19, 0x7f) 130*727a4006SBenjamin Gaignard #define av1_pic_height_pad AV1_DEC_REG(12, 26, 0x7) 131*727a4006SBenjamin Gaignard #define av1_pic_width_pad AV1_DEC_REG(12, 29, 0x7) 132*727a4006SBenjamin Gaignard 133*727a4006SBenjamin Gaignard #define av1_segment_e AV1_DEC_REG(13, 0, 0x1) 134*727a4006SBenjamin Gaignard #define av1_segment_upd_e AV1_DEC_REG(13, 1, 0x1) 135*727a4006SBenjamin Gaignard #define av1_segment_temp_upd_e AV1_DEC_REG(13, 2, 0x1) 136*727a4006SBenjamin Gaignard #define av1_comp_pred_var_ref0_av1 AV1_DEC_REG(13, 3, 0x7) 137*727a4006SBenjamin Gaignard #define av1_comp_pred_var_ref1_av1 AV1_DEC_REG(13, 6, 0x7) 138*727a4006SBenjamin Gaignard #define av1_lossless_e AV1_DEC_REG(13, 9, 0x1) 139*727a4006SBenjamin Gaignard #define av1_qp_delta_ch_ac_av1 AV1_DEC_REG(13, 11, 0x7f) 140*727a4006SBenjamin Gaignard #define av1_qp_delta_ch_dc_av1 AV1_DEC_REG(13, 18, 0x7f) 141*727a4006SBenjamin Gaignard #define av1_qp_delta_y_dc_av1 AV1_DEC_REG(13, 25, 0x7f) 142*727a4006SBenjamin Gaignard 143*727a4006SBenjamin Gaignard #define av1_quant_seg0 AV1_DEC_REG(14, 0, 0xff) 144*727a4006SBenjamin Gaignard #define av1_filt_level_seg0 AV1_DEC_REG(14, 8, 0x3f) 145*727a4006SBenjamin Gaignard #define av1_skip_seg0 AV1_DEC_REG(14, 14, 0x1) 146*727a4006SBenjamin Gaignard #define av1_refpic_seg0 AV1_DEC_REG(14, 15, 0xf) 147*727a4006SBenjamin Gaignard #define av1_filt_level_delta0_seg0 AV1_DEC_REG(14, 19, 0x7f) 148*727a4006SBenjamin Gaignard #define av1_filt_level0 AV1_DEC_REG(14, 26, 0x3f) 149*727a4006SBenjamin Gaignard 150*727a4006SBenjamin Gaignard #define av1_quant_seg1 AV1_DEC_REG(15, 0, 0xff) 151*727a4006SBenjamin Gaignard #define av1_filt_level_seg1 AV1_DEC_REG(15, 8, 0x3f) 152*727a4006SBenjamin Gaignard #define av1_skip_seg1 AV1_DEC_REG(15, 14, 0x1) 153*727a4006SBenjamin Gaignard #define av1_refpic_seg1 AV1_DEC_REG(15, 15, 0xf) 154*727a4006SBenjamin Gaignard #define av1_filt_level_delta0_seg1 AV1_DEC_REG(15, 19, 0x7f) 155*727a4006SBenjamin Gaignard #define av1_filt_level1 AV1_DEC_REG(15, 26, 0x3f) 156*727a4006SBenjamin Gaignard 157*727a4006SBenjamin Gaignard #define av1_quant_seg2 AV1_DEC_REG(16, 0, 0xff) 158*727a4006SBenjamin Gaignard #define av1_filt_level_seg2 AV1_DEC_REG(16, 8, 0x3f) 159*727a4006SBenjamin Gaignard #define av1_skip_seg2 AV1_DEC_REG(16, 14, 0x1) 160*727a4006SBenjamin Gaignard #define av1_refpic_seg2 AV1_DEC_REG(16, 15, 0xf) 161*727a4006SBenjamin Gaignard #define av1_filt_level_delta0_seg2 AV1_DEC_REG(16, 19, 0x7f) 162*727a4006SBenjamin Gaignard #define av1_filt_level2 AV1_DEC_REG(16, 26, 0x3f) 163*727a4006SBenjamin Gaignard 164*727a4006SBenjamin Gaignard #define av1_quant_seg3 AV1_DEC_REG(17, 0, 0xff) 165*727a4006SBenjamin Gaignard #define av1_filt_level_seg3 AV1_DEC_REG(17, 8, 0x3f) 166*727a4006SBenjamin Gaignard #define av1_skip_seg3 AV1_DEC_REG(17, 14, 0x1) 167*727a4006SBenjamin Gaignard #define av1_refpic_seg3 AV1_DEC_REG(17, 15, 0xf) 168*727a4006SBenjamin Gaignard #define av1_filt_level_delta0_seg3 AV1_DEC_REG(17, 19, 0x7f) 169*727a4006SBenjamin Gaignard #define av1_filt_level3 AV1_DEC_REG(17, 26, 0x3f) 170*727a4006SBenjamin Gaignard 171*727a4006SBenjamin Gaignard #define av1_quant_seg4 AV1_DEC_REG(18, 0, 0xff) 172*727a4006SBenjamin Gaignard #define av1_filt_level_seg4 AV1_DEC_REG(18, 8, 0x3f) 173*727a4006SBenjamin Gaignard #define av1_skip_seg4 AV1_DEC_REG(18, 14, 0x1) 174*727a4006SBenjamin Gaignard #define av1_refpic_seg4 AV1_DEC_REG(18, 15, 0xf) 175*727a4006SBenjamin Gaignard #define av1_filt_level_delta0_seg4 AV1_DEC_REG(18, 19, 0x7f) 176*727a4006SBenjamin Gaignard #define av1_lr_type AV1_DEC_REG(18, 26, 0x3f) 177*727a4006SBenjamin Gaignard 178*727a4006SBenjamin Gaignard #define av1_quant_seg5 AV1_DEC_REG(19, 0, 0xff) 179*727a4006SBenjamin Gaignard #define av1_filt_level_seg5 AV1_DEC_REG(19, 8, 0x3f) 180*727a4006SBenjamin Gaignard #define av1_skip_seg5 AV1_DEC_REG(19, 14, 0x1) 181*727a4006SBenjamin Gaignard #define av1_refpic_seg5 AV1_DEC_REG(19, 15, 0xf) 182*727a4006SBenjamin Gaignard #define av1_filt_level_delta0_seg5 AV1_DEC_REG(19, 19, 0x7f) 183*727a4006SBenjamin Gaignard #define av1_lr_unit_size AV1_DEC_REG(19, 26, 0x3f) 184*727a4006SBenjamin Gaignard 185*727a4006SBenjamin Gaignard #define av1_filt_level_delta1_seg0 AV1_DEC_REG(20, 0, 0x7f) 186*727a4006SBenjamin Gaignard #define av1_filt_level_delta2_seg0 AV1_DEC_REG(20, 7, 0x7f) 187*727a4006SBenjamin Gaignard #define av1_filt_level_delta3_seg0 AV1_DEC_REG(20, 14, 0x7f) 188*727a4006SBenjamin Gaignard #define av1_global_mv_seg0 AV1_DEC_REG(20, 21, 0x1) 189*727a4006SBenjamin Gaignard #define av1_mf1_last_offset AV1_DEC_REG(20, 22, 0x1ff) 190*727a4006SBenjamin Gaignard 191*727a4006SBenjamin Gaignard #define av1_filt_level_delta1_seg1 AV1_DEC_REG(21, 0, 0x7f) 192*727a4006SBenjamin Gaignard #define av1_filt_level_delta2_seg1 AV1_DEC_REG(21, 7, 0x7f) 193*727a4006SBenjamin Gaignard #define av1_filt_level_delta3_seg1 AV1_DEC_REG(21, 14, 0x7f) 194*727a4006SBenjamin Gaignard #define av1_global_mv_seg1 AV1_DEC_REG(21, 21, 0x1) 195*727a4006SBenjamin Gaignard #define av1_mf1_last2_offset AV1_DEC_REG(21, 22, 0x1ff) 196*727a4006SBenjamin Gaignard 197*727a4006SBenjamin Gaignard #define av1_filt_level_delta1_seg2 AV1_DEC_REG(22, 0, 0x7f) 198*727a4006SBenjamin Gaignard #define av1_filt_level_delta2_seg2 AV1_DEC_REG(22, 7, 0x7f) 199*727a4006SBenjamin Gaignard #define av1_filt_level_delta3_seg2 AV1_DEC_REG(22, 14, 0x7f) 200*727a4006SBenjamin Gaignard #define av1_global_mv_seg2 AV1_DEC_REG(22, 21, 0x1) 201*727a4006SBenjamin Gaignard #define av1_mf1_last3_offset AV1_DEC_REG(22, 22, 0x1ff) 202*727a4006SBenjamin Gaignard 203*727a4006SBenjamin Gaignard #define av1_filt_level_delta1_seg3 AV1_DEC_REG(23, 0, 0x7f) 204*727a4006SBenjamin Gaignard #define av1_filt_level_delta2_seg3 AV1_DEC_REG(23, 7, 0x7f) 205*727a4006SBenjamin Gaignard #define av1_filt_level_delta3_seg3 AV1_DEC_REG(23, 14, 0x7f) 206*727a4006SBenjamin Gaignard #define av1_global_mv_seg3 AV1_DEC_REG(23, 21, 0x1) 207*727a4006SBenjamin Gaignard #define av1_mf1_golden_offset AV1_DEC_REG(23, 22, 0x1ff) 208*727a4006SBenjamin Gaignard 209*727a4006SBenjamin Gaignard #define av1_filt_level_delta1_seg4 AV1_DEC_REG(24, 0, 0x7f) 210*727a4006SBenjamin Gaignard #define av1_filt_level_delta2_seg4 AV1_DEC_REG(24, 7, 0x7f) 211*727a4006SBenjamin Gaignard #define av1_filt_level_delta3_seg4 AV1_DEC_REG(24, 14, 0x7f) 212*727a4006SBenjamin Gaignard #define av1_global_mv_seg4 AV1_DEC_REG(24, 21, 0x1) 213*727a4006SBenjamin Gaignard #define av1_mf1_bwdref_offset AV1_DEC_REG(24, 22, 0x1ff) 214*727a4006SBenjamin Gaignard 215*727a4006SBenjamin Gaignard #define av1_filt_level_delta1_seg5 AV1_DEC_REG(25, 0, 0x7f) 216*727a4006SBenjamin Gaignard #define av1_filt_level_delta2_seg5 AV1_DEC_REG(25, 7, 0x7f) 217*727a4006SBenjamin Gaignard #define av1_filt_level_delta3_seg5 AV1_DEC_REG(25, 14, 0x7f) 218*727a4006SBenjamin Gaignard #define av1_global_mv_seg5 AV1_DEC_REG(25, 21, 0x1) 219*727a4006SBenjamin Gaignard #define av1_mf1_altref2_offset AV1_DEC_REG(25, 22, 0x1ff) 220*727a4006SBenjamin Gaignard 221*727a4006SBenjamin Gaignard #define av1_filt_level_delta1_seg6 AV1_DEC_REG(26, 0, 0x7f) 222*727a4006SBenjamin Gaignard #define av1_filt_level_delta2_seg6 AV1_DEC_REG(26, 7, 0x7f) 223*727a4006SBenjamin Gaignard #define av1_filt_level_delta3_seg6 AV1_DEC_REG(26, 14, 0x7f) 224*727a4006SBenjamin Gaignard #define av1_global_mv_seg6 AV1_DEC_REG(26, 21, 0x1) 225*727a4006SBenjamin Gaignard #define av1_mf1_altref_offset AV1_DEC_REG(26, 22, 0x1ff) 226*727a4006SBenjamin Gaignard 227*727a4006SBenjamin Gaignard #define av1_filt_level_delta1_seg7 AV1_DEC_REG(27, 0, 0x7f) 228*727a4006SBenjamin Gaignard #define av1_filt_level_delta2_seg7 AV1_DEC_REG(27, 7, 0x7f) 229*727a4006SBenjamin Gaignard #define av1_filt_level_delta3_seg7 AV1_DEC_REG(27, 14, 0x7f) 230*727a4006SBenjamin Gaignard #define av1_global_mv_seg7 AV1_DEC_REG(27, 21, 0x1) 231*727a4006SBenjamin Gaignard #define av1_mf2_last_offset AV1_DEC_REG(27, 22, 0x1ff) 232*727a4006SBenjamin Gaignard 233*727a4006SBenjamin Gaignard #define av1_cb_offset AV1_DEC_REG(28, 0, 0x1ff) 234*727a4006SBenjamin Gaignard #define av1_cb_luma_mult AV1_DEC_REG(28, 9, 0xff) 235*727a4006SBenjamin Gaignard #define av1_cb_mult AV1_DEC_REG(28, 17, 0xff) 236*727a4006SBenjamin Gaignard #define av1_quant_delta_v_dc AV1_DEC_REG(28, 25, 0x7f) 237*727a4006SBenjamin Gaignard 238*727a4006SBenjamin Gaignard #define av1_cr_offset AV1_DEC_REG(29, 0, 0x1ff) 239*727a4006SBenjamin Gaignard #define av1_cr_luma_mult AV1_DEC_REG(29, 9, 0xff) 240*727a4006SBenjamin Gaignard #define av1_cr_mult AV1_DEC_REG(29, 17, 0xff) 241*727a4006SBenjamin Gaignard #define av1_quant_delta_v_ac AV1_DEC_REG(29, 25, 0x7f) 242*727a4006SBenjamin Gaignard 243*727a4006SBenjamin Gaignard #define av1_filt_ref_adj_5 AV1_DEC_REG(30, 0, 0x7f) 244*727a4006SBenjamin Gaignard #define av1_filt_ref_adj_4 AV1_DEC_REG(30, 7, 0x7f) 245*727a4006SBenjamin Gaignard #define av1_filt_mb_adj_1 AV1_DEC_REG(30, 14, 0x7f) 246*727a4006SBenjamin Gaignard #define av1_filt_mb_adj_0 AV1_DEC_REG(30, 21, 0x7f) 247*727a4006SBenjamin Gaignard #define av1_filt_sharpness AV1_DEC_REG(30, 28, 0x7) 248*727a4006SBenjamin Gaignard 249*727a4006SBenjamin Gaignard #define av1_quant_seg6 AV1_DEC_REG(31, 0, 0xff) 250*727a4006SBenjamin Gaignard #define av1_filt_level_seg6 AV1_DEC_REG(31, 8, 0x3f) 251*727a4006SBenjamin Gaignard #define av1_skip_seg6 AV1_DEC_REG(31, 14, 0x1) 252*727a4006SBenjamin Gaignard #define av1_refpic_seg6 AV1_DEC_REG(31, 15, 0xf) 253*727a4006SBenjamin Gaignard #define av1_filt_level_delta0_seg6 AV1_DEC_REG(31, 19, 0x7f) 254*727a4006SBenjamin Gaignard #define av1_skip_ref0 AV1_DEC_REG(31, 26, 0xf) 255*727a4006SBenjamin Gaignard 256*727a4006SBenjamin Gaignard #define av1_quant_seg7 AV1_DEC_REG(32, 0, 0xff) 257*727a4006SBenjamin Gaignard #define av1_filt_level_seg7 AV1_DEC_REG(32, 8, 0x3f) 258*727a4006SBenjamin Gaignard #define av1_skip_seg7 AV1_DEC_REG(32, 14, 0x1) 259*727a4006SBenjamin Gaignard #define av1_refpic_seg7 AV1_DEC_REG(32, 15, 0xf) 260*727a4006SBenjamin Gaignard #define av1_filt_level_delta0_seg7 AV1_DEC_REG(32, 19, 0x7f) 261*727a4006SBenjamin Gaignard #define av1_skip_ref1 AV1_DEC_REG(32, 26, 0xf) 262*727a4006SBenjamin Gaignard 263*727a4006SBenjamin Gaignard #define av1_ref0_height AV1_DEC_REG(33, 0, 0xffff) 264*727a4006SBenjamin Gaignard #define av1_ref0_width AV1_DEC_REG(33, 16, 0xffff) 265*727a4006SBenjamin Gaignard 266*727a4006SBenjamin Gaignard #define av1_ref1_height AV1_DEC_REG(34, 0, 0xffff) 267*727a4006SBenjamin Gaignard #define av1_ref1_width AV1_DEC_REG(34, 16, 0xffff) 268*727a4006SBenjamin Gaignard 269*727a4006SBenjamin Gaignard #define av1_ref2_height AV1_DEC_REG(35, 0, 0xffff) 270*727a4006SBenjamin Gaignard #define av1_ref2_width AV1_DEC_REG(35, 16, 0xffff) 271*727a4006SBenjamin Gaignard 272*727a4006SBenjamin Gaignard #define av1_ref0_ver_scale AV1_DEC_REG(36, 0, 0xffff) 273*727a4006SBenjamin Gaignard #define av1_ref0_hor_scale AV1_DEC_REG(36, 16, 0xffff) 274*727a4006SBenjamin Gaignard 275*727a4006SBenjamin Gaignard #define av1_ref1_ver_scale AV1_DEC_REG(37, 0, 0xffff) 276*727a4006SBenjamin Gaignard #define av1_ref1_hor_scale AV1_DEC_REG(37, 16, 0xffff) 277*727a4006SBenjamin Gaignard 278*727a4006SBenjamin Gaignard #define av1_ref2_ver_scale AV1_DEC_REG(38, 0, 0xffff) 279*727a4006SBenjamin Gaignard #define av1_ref2_hor_scale AV1_DEC_REG(38, 16, 0xffff) 280*727a4006SBenjamin Gaignard 281*727a4006SBenjamin Gaignard #define av1_ref3_ver_scale AV1_DEC_REG(39, 0, 0xffff) 282*727a4006SBenjamin Gaignard #define av1_ref3_hor_scale AV1_DEC_REG(39, 16, 0xffff) 283*727a4006SBenjamin Gaignard 284*727a4006SBenjamin Gaignard #define av1_ref4_ver_scale AV1_DEC_REG(40, 0, 0xffff) 285*727a4006SBenjamin Gaignard #define av1_ref4_hor_scale AV1_DEC_REG(40, 16, 0xffff) 286*727a4006SBenjamin Gaignard 287*727a4006SBenjamin Gaignard #define av1_ref5_ver_scale AV1_DEC_REG(41, 0, 0xffff) 288*727a4006SBenjamin Gaignard #define av1_ref5_hor_scale AV1_DEC_REG(41, 16, 0xffff) 289*727a4006SBenjamin Gaignard 290*727a4006SBenjamin Gaignard #define av1_ref6_ver_scale AV1_DEC_REG(42, 0, 0xffff) 291*727a4006SBenjamin Gaignard #define av1_ref6_hor_scale AV1_DEC_REG(42, 16, 0xffff) 292*727a4006SBenjamin Gaignard 293*727a4006SBenjamin Gaignard #define av1_ref3_height AV1_DEC_REG(43, 0, 0xffff) 294*727a4006SBenjamin Gaignard #define av1_ref3_width AV1_DEC_REG(43, 16, 0xffff) 295*727a4006SBenjamin Gaignard 296*727a4006SBenjamin Gaignard #define av1_ref4_height AV1_DEC_REG(44, 0, 0xffff) 297*727a4006SBenjamin Gaignard #define av1_ref4_width AV1_DEC_REG(44, 16, 0xffff) 298*727a4006SBenjamin Gaignard 299*727a4006SBenjamin Gaignard #define av1_ref5_height AV1_DEC_REG(45, 0, 0xffff) 300*727a4006SBenjamin Gaignard #define av1_ref5_width AV1_DEC_REG(45, 16, 0xffff) 301*727a4006SBenjamin Gaignard 302*727a4006SBenjamin Gaignard #define av1_ref6_height AV1_DEC_REG(46, 0, 0xffff) 303*727a4006SBenjamin Gaignard #define av1_ref6_width AV1_DEC_REG(46, 16, 0xffff) 304*727a4006SBenjamin Gaignard 305*727a4006SBenjamin Gaignard #define av1_mf2_last2_offset AV1_DEC_REG(47, 0, 0x1ff) 306*727a4006SBenjamin Gaignard #define av1_mf2_last3_offset AV1_DEC_REG(47, 9, 0x1ff) 307*727a4006SBenjamin Gaignard #define av1_mf2_golden_offset AV1_DEC_REG(47, 18, 0x1ff) 308*727a4006SBenjamin Gaignard #define av1_qmlevel_y AV1_DEC_REG(47, 27, 0xf) 309*727a4006SBenjamin Gaignard 310*727a4006SBenjamin Gaignard #define av1_mf2_bwdref_offset AV1_DEC_REG(48, 0, 0x1ff) 311*727a4006SBenjamin Gaignard #define av1_mf2_altref2_offset AV1_DEC_REG(48, 9, 0x1ff) 312*727a4006SBenjamin Gaignard #define av1_mf2_altref_offset AV1_DEC_REG(48, 18, 0x1ff) 313*727a4006SBenjamin Gaignard #define av1_qmlevel_u AV1_DEC_REG(48, 27, 0xf) 314*727a4006SBenjamin Gaignard 315*727a4006SBenjamin Gaignard #define av1_filt_ref_adj_6 AV1_DEC_REG(49, 0, 0x7f) 316*727a4006SBenjamin Gaignard #define av1_filt_ref_adj_7 AV1_DEC_REG(49, 7, 0x7f) 317*727a4006SBenjamin Gaignard #define av1_qmlevel_v AV1_DEC_REG(49, 14, 0xf) 318*727a4006SBenjamin Gaignard 319*727a4006SBenjamin Gaignard #define av1_superres_chroma_step AV1_DEC_REG(51, 0, 0x3fff) 320*727a4006SBenjamin Gaignard #define av1_superres_luma_step AV1_DEC_REG(51, 14, 0x3fff) 321*727a4006SBenjamin Gaignard 322*727a4006SBenjamin Gaignard #define av1_superres_init_chroma_subpel_x AV1_DEC_REG(52, 0, 0x3fff) 323*727a4006SBenjamin Gaignard #define av1_superres_init_luma_subpel_x AV1_DEC_REG(52, 14, 0x3fff) 324*727a4006SBenjamin Gaignard 325*727a4006SBenjamin Gaignard #define av1_cdef_chroma_secondary_strength AV1_DEC_REG(53, 0, 0xffff) 326*727a4006SBenjamin Gaignard #define av1_cdef_luma_secondary_strength AV1_DEC_REG(53, 16, 0xffff) 327*727a4006SBenjamin Gaignard 328*727a4006SBenjamin Gaignard #define av1_apf_threshold AV1_DEC_REG(55, 0, 0xffff) 329*727a4006SBenjamin Gaignard #define av1_apf_single_pu_mode AV1_DEC_REG(55, 30, 0x1) 330*727a4006SBenjamin Gaignard #define av1_apf_disable AV1_DEC_REG(55, 30, 0x1) 331*727a4006SBenjamin Gaignard 332*727a4006SBenjamin Gaignard #define av1_dec_max_burst AV1_DEC_REG(58, 0, 0xff) 333*727a4006SBenjamin Gaignard #define av1_dec_buswidth AV1_DEC_REG(58, 8, 0x7) 334*727a4006SBenjamin Gaignard #define av1_dec_multicore_mode AV1_DEC_REG(58, 11, 0x3) 335*727a4006SBenjamin Gaignard #define av1_dec_axi_wd_id_e AV1_DEC_REG(58, 13, 0x1) 336*727a4006SBenjamin Gaignard #define av1_dec_axi_rd_id_e AV1_DEC_REG(58, 14, 0x1) 337*727a4006SBenjamin Gaignard #define av1_dec_mc_polltime AV1_DEC_REG(58, 17, 0x3ff) 338*727a4006SBenjamin Gaignard #define av1_dec_mc_pollmode AV1_DEC_REG(58, 27, 0x3) 339*727a4006SBenjamin Gaignard 340*727a4006SBenjamin Gaignard #define av1_filt_ref_adj_3 AV1_DEC_REG(59, 0, 0x3f) 341*727a4006SBenjamin Gaignard #define av1_filt_ref_adj_2 AV1_DEC_REG(59, 7, 0x3f) 342*727a4006SBenjamin Gaignard #define av1_filt_ref_adj_1 AV1_DEC_REG(59, 14, 0x3f) 343*727a4006SBenjamin Gaignard #define av1_filt_ref_adj_0 AV1_DEC_REG(59, 21, 0x3f) 344*727a4006SBenjamin Gaignard #define av1_ref0_sign_bias AV1_DEC_REG(59, 28, 0x1) 345*727a4006SBenjamin Gaignard #define av1_ref1_sign_bias AV1_DEC_REG(59, 29, 0x1) 346*727a4006SBenjamin Gaignard #define av1_ref2_sign_bias AV1_DEC_REG(59, 30, 0x1) 347*727a4006SBenjamin Gaignard #define av1_ref3_sign_bias AV1_DEC_REG(59, 31, 0x1) 348*727a4006SBenjamin Gaignard 349*727a4006SBenjamin Gaignard #define av1_cur_last_roffset AV1_DEC_REG(184, 0, 0x1ff) 350*727a4006SBenjamin Gaignard #define av1_cur_last_offset AV1_DEC_REG(184, 9, 0x1ff) 351*727a4006SBenjamin Gaignard #define av1_mf3_last_offset AV1_DEC_REG(184, 18, 0x1ff) 352*727a4006SBenjamin Gaignard #define av1_ref0_gm_mode AV1_DEC_REG(184, 27, 0x3) 353*727a4006SBenjamin Gaignard 354*727a4006SBenjamin Gaignard #define av1_cur_last2_roffset AV1_DEC_REG(185, 0, 0x1ff) 355*727a4006SBenjamin Gaignard #define av1_cur_last2_offset AV1_DEC_REG(185, 9, 0x1ff) 356*727a4006SBenjamin Gaignard #define av1_mf3_last2_offset AV1_DEC_REG(185, 18, 0x1ff) 357*727a4006SBenjamin Gaignard #define av1_ref1_gm_mode AV1_DEC_REG(185, 27, 0x3) 358*727a4006SBenjamin Gaignard 359*727a4006SBenjamin Gaignard #define av1_cur_last3_roffset AV1_DEC_REG(186, 0, 0x1ff) 360*727a4006SBenjamin Gaignard #define av1_cur_last3_offset AV1_DEC_REG(186, 9, 0x1ff) 361*727a4006SBenjamin Gaignard #define av1_mf3_last3_offset AV1_DEC_REG(186, 18, 0x1ff) 362*727a4006SBenjamin Gaignard #define av1_ref2_gm_mode AV1_DEC_REG(186, 27, 0x3) 363*727a4006SBenjamin Gaignard 364*727a4006SBenjamin Gaignard #define av1_cur_golden_roffset AV1_DEC_REG(187, 0, 0x1ff) 365*727a4006SBenjamin Gaignard #define av1_cur_golden_offset AV1_DEC_REG(187, 9, 0x1ff) 366*727a4006SBenjamin Gaignard #define av1_mf3_golden_offset AV1_DEC_REG(187, 18, 0x1ff) 367*727a4006SBenjamin Gaignard #define av1_ref3_gm_mode AV1_DEC_REG(187, 27, 0x3) 368*727a4006SBenjamin Gaignard 369*727a4006SBenjamin Gaignard #define av1_cur_bwdref_roffset AV1_DEC_REG(188, 0, 0x1ff) 370*727a4006SBenjamin Gaignard #define av1_cur_bwdref_offset AV1_DEC_REG(188, 9, 0x1ff) 371*727a4006SBenjamin Gaignard #define av1_mf3_bwdref_offset AV1_DEC_REG(188, 18, 0x1ff) 372*727a4006SBenjamin Gaignard #define av1_ref4_gm_mode AV1_DEC_REG(188, 27, 0x3) 373*727a4006SBenjamin Gaignard 374*727a4006SBenjamin Gaignard #define av1_cur_altref2_roffset AV1_DEC_REG(257, 0, 0x1ff) 375*727a4006SBenjamin Gaignard #define av1_cur_altref2_offset AV1_DEC_REG(257, 9, 0x1ff) 376*727a4006SBenjamin Gaignard #define av1_mf3_altref2_offset AV1_DEC_REG(257, 18, 0x1ff) 377*727a4006SBenjamin Gaignard #define av1_ref5_gm_mode AV1_DEC_REG(257, 27, 0x3) 378*727a4006SBenjamin Gaignard 379*727a4006SBenjamin Gaignard #define av1_strm_buffer_len AV1_DEC_REG(258, 0, 0xffffffff) 380*727a4006SBenjamin Gaignard 381*727a4006SBenjamin Gaignard #define av1_strm_start_offset AV1_DEC_REG(259, 0, 0xffffffff) 382*727a4006SBenjamin Gaignard 383*727a4006SBenjamin Gaignard #define av1_ppd_blend_exist AV1_DEC_REG(260, 21, 0x1) 384*727a4006SBenjamin Gaignard #define av1_ppd_dith_exist AV1_DEC_REG(260, 23, 0x1) 385*727a4006SBenjamin Gaignard #define av1_ablend_crop_e AV1_DEC_REG(260, 24, 0x1) 386*727a4006SBenjamin Gaignard #define av1_pp_format_p010_e AV1_DEC_REG(260, 25, 0x1) 387*727a4006SBenjamin Gaignard #define av1_pp_format_customer1_e AV1_DEC_REG(260, 26, 0x1) 388*727a4006SBenjamin Gaignard #define av1_pp_crop_exist AV1_DEC_REG(260, 27, 0x1) 389*727a4006SBenjamin Gaignard #define av1_pp_up_level AV1_DEC_REG(260, 28, 0x1) 390*727a4006SBenjamin Gaignard #define av1_pp_down_level AV1_DEC_REG(260, 29, 0x3) 391*727a4006SBenjamin Gaignard #define av1_pp_exist AV1_DEC_REG(260, 31, 0x1) 392*727a4006SBenjamin Gaignard 393*727a4006SBenjamin Gaignard #define av1_cur_altref_roffset AV1_DEC_REG(262, 0, 0x1ff) 394*727a4006SBenjamin Gaignard #define av1_cur_altref_offset AV1_DEC_REG(262, 9, 0x1ff) 395*727a4006SBenjamin Gaignard #define av1_mf3_altref_offset AV1_DEC_REG(262, 18, 0x1ff) 396*727a4006SBenjamin Gaignard #define av1_ref6_gm_mode AV1_DEC_REG(262, 27, 0x3) 397*727a4006SBenjamin Gaignard 398*727a4006SBenjamin Gaignard #define av1_cdef_luma_primary_strength AV1_DEC_REG(263, 0, 0xffffffff) 399*727a4006SBenjamin Gaignard 400*727a4006SBenjamin Gaignard #define av1_cdef_chroma_primary_strength AV1_DEC_REG(264, 0, 0xffffffff) 401*727a4006SBenjamin Gaignard 402*727a4006SBenjamin Gaignard #define av1_axi_arqos AV1_DEC_REG(265, 0, 0xf) 403*727a4006SBenjamin Gaignard #define av1_axi_awqos AV1_DEC_REG(265, 4, 0xf) 404*727a4006SBenjamin Gaignard #define av1_axi_wr_ostd_threshold AV1_DEC_REG(265, 8, 0x3ff) 405*727a4006SBenjamin Gaignard #define av1_axi_rd_ostd_threshold AV1_DEC_REG(265, 18, 0x3ff) 406*727a4006SBenjamin Gaignard #define av1_axi_wr_4k_dis AV1_DEC_REG(265, 31, 0x1) 407*727a4006SBenjamin Gaignard 408*727a4006SBenjamin Gaignard #define av1_128bit_mode AV1_DEC_REG(266, 5, 0x1) 409*727a4006SBenjamin Gaignard #define av1_wr_shaper_bypass AV1_DEC_REG(266, 10, 0x1) 410*727a4006SBenjamin Gaignard #define av1_error_conceal_e AV1_DEC_REG(266, 30, 0x1) 411*727a4006SBenjamin Gaignard 412*727a4006SBenjamin Gaignard #define av1_superres_chroma_step_invra AV1_DEC_REG(298, 0, 0xffff) 413*727a4006SBenjamin Gaignard #define av1_superres_luma_step_invra AV1_DEC_REG(298, 16, 0xffff) 414*727a4006SBenjamin Gaignard 415*727a4006SBenjamin Gaignard #define av1_dec_alignment AV1_DEC_REG(314, 0, 0xffff) 416*727a4006SBenjamin Gaignard 417*727a4006SBenjamin Gaignard #define av1_ext_timeout_cycles AV1_DEC_REG(318, 0, 0x7fffffff) 418*727a4006SBenjamin Gaignard #define av1_ext_timeout_override_e AV1_DEC_REG(318, 31, 0x1) 419*727a4006SBenjamin Gaignard 420*727a4006SBenjamin Gaignard #define av1_timeout_cycles AV1_DEC_REG(319, 0, 0x7fffffff) 421*727a4006SBenjamin Gaignard #define av1_timeout_override_e AV1_DEC_REG(319, 31, 0x1) 422*727a4006SBenjamin Gaignard 423*727a4006SBenjamin Gaignard #define av1_pp_out_e AV1_DEC_REG(320, 0, 0x1) 424*727a4006SBenjamin Gaignard #define av1_pp_cr_first AV1_DEC_REG(320, 1, 0x1) 425*727a4006SBenjamin Gaignard #define av1_pp_out_mode AV1_DEC_REG(320, 2, 0x1) 426*727a4006SBenjamin Gaignard #define av1_pp_out_tile_e AV1_DEC_REG(320, 3, 0x1) 427*727a4006SBenjamin Gaignard #define av1_pp_status AV1_DEC_REG(320, 4, 0xf) 428*727a4006SBenjamin Gaignard #define av1_pp_in_blk_size AV1_DEC_REG(320, 8, 0x7) 429*727a4006SBenjamin Gaignard #define av1_pp_out_p010_fmt AV1_DEC_REG(320, 11, 0x3) 430*727a4006SBenjamin Gaignard #define av1_pp_out_rgb_fmt AV1_DEC_REG(320, 13, 0x1f) 431*727a4006SBenjamin Gaignard #define av1_rgb_range_max AV1_DEC_REG(320, 18, 0xfff) 432*727a4006SBenjamin Gaignard #define av1_pp_rgb_planar AV1_DEC_REG(320, 30, 0x1) 433*727a4006SBenjamin Gaignard 434*727a4006SBenjamin Gaignard #define av1_scale_hratio AV1_DEC_REG(322, 0, 0x3ffff) 435*727a4006SBenjamin Gaignard #define av1_pp_out_format AV1_DEC_REG(322, 18, 0x1f) 436*727a4006SBenjamin Gaignard #define av1_ver_scale_mode AV1_DEC_REG(322, 23, 0x3) 437*727a4006SBenjamin Gaignard #define av1_hor_scale_mode AV1_DEC_REG(322, 25, 0x3) 438*727a4006SBenjamin Gaignard #define av1_pp_in_format AV1_DEC_REG(322, 27, 0x1f) 439*727a4006SBenjamin Gaignard 440*727a4006SBenjamin Gaignard #define av1_pp_out_c_stride AV1_DEC_REG(329, 0, 0xffff) 441*727a4006SBenjamin Gaignard #define av1_pp_out_y_stride AV1_DEC_REG(329, 16, 0xffff) 442*727a4006SBenjamin Gaignard 443*727a4006SBenjamin Gaignard #define av1_pp_in_height AV1_DEC_REG(331, 0, 0xffff) 444*727a4006SBenjamin Gaignard #define av1_pp_in_width AV1_DEC_REG(331, 16, 0xffff) 445*727a4006SBenjamin Gaignard 446*727a4006SBenjamin Gaignard #define av1_pp_out_height AV1_DEC_REG(332, 0, 0xffff) 447*727a4006SBenjamin Gaignard #define av1_pp_out_width AV1_DEC_REG(332, 16, 0xffff) 448*727a4006SBenjamin Gaignard 449*727a4006SBenjamin Gaignard #define av1_pp1_dup_ver AV1_DEC_REG(394, 0, 0xff) 450*727a4006SBenjamin Gaignard #define av1_pp1_dup_hor AV1_DEC_REG(394, 8, 0xff) 451*727a4006SBenjamin Gaignard #define av1_pp0_dup_ver AV1_DEC_REG(394, 16, 0xff) 452*727a4006SBenjamin Gaignard #define av1_pp0_dup_hor AV1_DEC_REG(394, 24, 0xff) 453*727a4006SBenjamin Gaignard 454*727a4006SBenjamin Gaignard #define AV1_TILE_OUT_LU (AV1_SWREG(65)) 455*727a4006SBenjamin Gaignard #define AV1_REFERENCE_Y(i) (AV1_SWREG(67) + ((i) * 0x8)) 456*727a4006SBenjamin Gaignard #define AV1_SEGMENTATION (AV1_SWREG(81)) 457*727a4006SBenjamin Gaignard #define AV1_GLOBAL_MODEL (AV1_SWREG(83)) 458*727a4006SBenjamin Gaignard #define AV1_CDEF_COL (AV1_SWREG(85)) 459*727a4006SBenjamin Gaignard #define AV1_SR_COL (AV1_SWREG(89)) 460*727a4006SBenjamin Gaignard #define AV1_LR_COL (AV1_SWREG(91)) 461*727a4006SBenjamin Gaignard #define AV1_FILM_GRAIN (AV1_SWREG(95)) 462*727a4006SBenjamin Gaignard #define AV1_TILE_OUT_CH (AV1_SWREG(99)) 463*727a4006SBenjamin Gaignard #define AV1_REFERENCE_CB(i) (AV1_SWREG(101) + ((i) * 0x8)) 464*727a4006SBenjamin Gaignard #define AV1_TILE_OUT_MV (AV1_SWREG(133)) 465*727a4006SBenjamin Gaignard #define AV1_REFERENCE_MV(i) (AV1_SWREG(135) + ((i) * 0x8)) 466*727a4006SBenjamin Gaignard #define AV1_TILE_BASE (AV1_SWREG(167)) 467*727a4006SBenjamin Gaignard #define AV1_INPUT_STREAM (AV1_SWREG(169)) 468*727a4006SBenjamin Gaignard #define AV1_PROP_TABLE_OUT (AV1_SWREG(171)) 469*727a4006SBenjamin Gaignard #define AV1_PROP_TABLE (AV1_SWREG(173)) 470*727a4006SBenjamin Gaignard #define AV1_MC_SYNC_CURR (AV1_SWREG(175)) 471*727a4006SBenjamin Gaignard #define AV1_MC_SYNC_LEFT (AV1_SWREG(177)) 472*727a4006SBenjamin Gaignard #define AV1_DB_DATA_COL (AV1_SWREG(179)) 473*727a4006SBenjamin Gaignard #define AV1_DB_CTRL_COL (AV1_SWREG(183)) 474*727a4006SBenjamin Gaignard #define AV1_PP_OUT_LU (AV1_SWREG(326)) 475*727a4006SBenjamin Gaignard #define AV1_PP_OUT_CH (AV1_SWREG(328)) 476*727a4006SBenjamin Gaignard 477*727a4006SBenjamin Gaignard #endif /* _ROCKCHIP_VPU981_REGS_H_ */ 478