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/openbmc/linux/drivers/clk/qcom/
H A Dgpucc-sc7280.c30 { 249600000, 2000000000, 0 },
34 .offset = 0x0,
52 .l = 0x1A,
53 .alpha = 0xAAA,
54 .config_ctl_val = 0x20485699,
55 .config_ctl_hi_val = 0x00002261,
56 .config_ctl_hi1_val = 0x329A299C,
57 .user_ctl_val = 0x00000001,
58 .user_ctl_hi_val = 0x00000805,
59 .user_ctl_hi1_val = 0x00000000,
[all …]
H A Dgpucc-sm8350.c38 { 249600000, 1750000000, 0 },
42 .l = 0x18,
43 .alpha = 0x6000,
44 .config_ctl_val = 0x20485699,
45 .config_ctl_hi_val = 0x00002261,
46 .config_ctl_hi1_val = 0x2a9a699c,
47 .test_ctl_val = 0x00000000,
48 .test_ctl_hi_val = 0x00000000,
49 .test_ctl_hi1_val = 0x01800000,
50 .user_ctl_val = 0x00000000,
[all …]
H A Dgpucc-sc8280xp.c41 { 249600000, 1800000000, 0 },
45 .l = 0x1c,
46 .alpha = 0xa555,
47 .config_ctl_val = 0x20485699,
48 .config_ctl_hi_val = 0x00002261,
49 .config_ctl_hi1_val = 0x2a9a699c,
50 .test_ctl_val = 0x00000000,
51 .test_ctl_hi_val = 0x00000000,
52 .test_ctl_hi1_val = 0x01800000,
53 .user_ctl_val = 0x00000000,
[all …]
H A Ddispcc-sm8450.c52 #define DISP_CC_MISC_CMD 0xF000
75 { 249600000, 2000000000, 0 },
79 .l = 0xD,
80 .alpha = 0x6492,
81 .config_ctl_val = 0x20485699,
82 .config_ctl_hi_val = 0x00182261,
83 .config_ctl_hi1_val = 0x32AA299C,
84 .user_ctl_val = 0x00000000,
85 .user_ctl_hi_val = 0x00000805,
89 .offset = 0x0,
[all …]
H A Ddispcc-sm8550.c52 #define DISP_CC_MISC_CMD 0xF000
75 { 249600000, 2000000000, 0 },
79 .l = 0xd,
80 .alpha = 0x6492,
81 .config_ctl_val = 0x20485699,
82 .config_ctl_hi_val = 0x00182261,
83 .config_ctl_hi1_val = 0x82aa299c,
84 .test_ctl_val = 0x00000000,
85 .test_ctl_hi_val = 0x00000003,
86 .test_ctl_hi1_val = 0x00009000,
[all …]
/openbmc/linux/drivers/media/rc/keymaps/
H A Drc-tanix-tx3mini.c12 { 0x8051, KEY_POWER },
13 { 0x804d, KEY_MUTE },
15 { 0x8009, KEY_RED },
16 { 0x8011, KEY_GREEN },
17 { 0x8054, KEY_YELLOW },
18 { 0x804f, KEY_BLUE },
20 { 0x8056, KEY_VOLUMEDOWN },
21 { 0x80bd, KEY_PREVIOUS },
22 { 0x80bb, KEY_NEXT },
23 { 0x804e, KEY_VOLUMEUP },
[all …]
H A Drc-beelink-gs1.c14 * { 0x40400d, KEY_TV },
15 * { 0x80f1, KEY_TV },
16 * { 0x80f3, KEY_TV },
17 * { 0x80f4, KEY_TV },
20 { 0x8051, KEY_POWER },
21 { 0x804d, KEY_MUTE },
22 { 0x8040, KEY_CONFIG },
24 { 0x8026, KEY_UP },
25 { 0x8028, KEY_DOWN },
26 { 0x8025, KEY_LEFT },
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Damlogic,meson8-pinctrl-cbus.yaml32 "^bank@[0-9a-z]+$":
65 reg = <0x80b0 0x28>,
66 <0x80e8 0x18>,
67 <0x8120 0x18>,
68 <0x8030 0x30>;
72 gpio-ranges = <&pinctrl_cbus 0 0 120>;
/openbmc/linux/drivers/net/phy/
H A Dadin1100.c17 #define PHY_ID_ADIN1100 0x0283bc81
18 #define PHY_ID_ADIN1110 0x0283bc91
19 #define PHY_ID_ADIN2111 0x0283bca1
21 #define ADIN_FORCED_MODE 0x8000
22 #define ADIN_FORCED_MODE_EN BIT(0)
24 #define ADIN_CRSM_SFT_RST 0x8810
25 #define ADIN_CRSM_SFT_RST_EN BIT(0)
27 #define ADIN_CRSM_SFT_PD_CNTRL 0x8812
28 #define ADIN_CRSM_SFT_PD_CNTRL_EN BIT(0)
30 #define ADIN_AN_PHY_INST_STATUS 0x8030
[all …]
/openbmc/linux/sound/isa/sb/
H A Demu8000.c99 unsigned right_bit = (mode & EMU8000_RAM_RIGHT) ? 0x01000000 : 0; in snd_emu8000_dma_chan()
102 EMU8000_CCCA_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
103 EMU8000_DCYSUSV_WRITE(emu, ch, 0x807F); in snd_emu8000_dma_chan()
106 EMU8000_DCYSUSV_WRITE(emu, ch, 0x80); in snd_emu8000_dma_chan()
107 EMU8000_VTFT_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
108 EMU8000_CVCF_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
109 EMU8000_PTRX_WRITE(emu, ch, 0x40000000); in snd_emu8000_dma_chan()
110 EMU8000_CPF_WRITE(emu, ch, 0x40000000); in snd_emu8000_dma_chan()
111 EMU8000_PSST_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
112 EMU8000_CSL_WRITE(emu, ch, 0); in snd_emu8000_dma_chan()
[all …]
/openbmc/linux/include/video/
H A Dpermedia2.h17 #define PM2_REGS_SIZE 0x10000
19 #define PM2TAG(r) (u32 )(((r)-0x8000)>>3)
25 #define PM2R_RESET_STATUS 0x0000
26 #define PM2R_IN_FIFO_SPACE 0x0018
27 #define PM2R_OUT_FIFO_WORDS 0x0020
28 #define PM2R_APERTURE_ONE 0x0050
29 #define PM2R_APERTURE_TWO 0x0058
30 #define PM2R_FIFO_DISCON 0x0068
31 #define PM2R_CHIP_CONFIG 0x0070
33 #define PM2R_REBOOT 0x1000
[all …]
/openbmc/u-boot/drivers/cpu/
H A Dmpc83xx_cpu.c63 /* Upper 12 bits of PARTID field (bits 0-23 in SPRIDR) */ in determine_family()
64 const u32 PARTID_FAMILY_MASK = 0xFFF00000; in determine_family()
67 case 0x810: in determine_family()
68 case 0x811: in determine_family()
71 case 0x80B: in determine_family()
74 case 0x806: in determine_family()
77 case 0x803: in determine_family()
80 case 0x804: in determine_family()
83 case 0x80C: in determine_family()
99 const u32 PCR_UPPER_MASK = 0xFFFF0000; in determine_type()
[all …]
/openbmc/linux/drivers/media/usb/gspca/gl860/
H A Dgl860.c38 static s32 AC50Hz = 0xff;
40 MODULE_PARM_DESC(AC50Hz, " Does AC power frequency is 50Hz? (0/1)");
96 return 0; in sd_s_ctrl()
113 0, sd->vmax.brightness, 1, in sd_init_controls()
118 0, sd->vmax.contrast, 1, in sd_init_controls()
123 0, sd->vmax.saturation, 1, in sd_init_controls()
128 0, sd->vmax.hue, 1, sd->vcur.hue); in sd_init_controls()
132 0, sd->vmax.gamma, 1, sd->vcur.gamma); in sd_init_controls()
136 0, sd->vmax.mirror, 1, sd->vcur.mirror); in sd_init_controls()
140 0, sd->vmax.flip, 1, sd->vcur.flip); in sd_init_controls()
[all …]
H A Dgl860-mi2020.c12 static u8 dat_wbal1[] = {0x8c, 0xa2, 0x0c};
14 static u8 dat_bright1[] = {0x8c, 0xa2, 0x06};
15 static u8 dat_bright3[] = {0x8c, 0xa1, 0x02};
16 static u8 dat_bright4[] = {0x90, 0x00, 0x0f};
17 static u8 dat_bright5[] = {0x8c, 0xa1, 0x03};
18 static u8 dat_bright6[] = {0x90, 0x00, 0x05};
20 static u8 dat_hvflip1[] = {0x8c, 0x27, 0x19};
21 static u8 dat_hvflip3[] = {0x8c, 0x27, 0x3b};
22 static u8 dat_hvflip5[] = {0x8c, 0xa1, 0x03};
23 static u8 dat_hvflip6[] = {0x90, 0x00, 0x06};
[all …]
/openbmc/linux/drivers/net/wireless/intersil/orinoco/
H A Dorinoco_nortel.c53 #define COR_OFFSET (0xe0) /* COR attribute offset of Prism2 PC card */
72 iowrite16(0x80, card->attr_io + COR_OFFSET); in orinoco_nortel_cor_reset()
76 iowrite16(0, card->attr_io + COR_OFFSET); in orinoco_nortel_cor_reset()
77 iowrite16(0, card->attr_io + COR_OFFSET); in orinoco_nortel_cor_reset()
85 iowrite16(0x228, card->bridge_io + 2); in orinoco_nortel_cor_reset()
87 return 0; in orinoco_nortel_cor_reset()
100 iowrite16(0x118, card->bridge_io + 2); in orinoco_nortel_hw_init()
101 iowrite16(0x108, card->bridge_io + 2); in orinoco_nortel_hw_init()
103 iowrite16(0x8, card->bridge_io + 2); in orinoco_nortel_hw_init()
104 for (i = 0; i < 30; i++) { in orinoco_nortel_hw_init()
[all …]
/openbmc/linux/include/linux/mfd/mt6332/
H A Dregisters.h10 #define MT6332_HWCID 0x8000
11 #define MT6332_SWCID 0x8002
12 #define MT6332_TOP_CON 0x8004
13 #define MT6332_DDR_VREF_AP_CON 0x8006
14 #define MT6332_DDR_VREF_DQ_CON 0x8008
15 #define MT6332_DDR_VREF_CA_CON 0x800A
16 #define MT6332_TEST_OUT 0x800C
17 #define MT6332_TEST_CON0 0x800E
18 #define MT6332_TEST_CON1 0x8010
19 #define MT6332_TESTMODE_SW 0x8012
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dni.c71 0x98fc,
72 0x98f0,
73 0x9834,
74 0x9838,
75 0x9870,
76 0x9874,
77 0x8a14,
78 0x8b24,
79 0x8bcc,
80 0x8b10,
[all …]
/openbmc/linux/drivers/net/wireless/intersil/hostap/
H A Dhostap_plx.c49 #define COR_SRESET 0x80
50 #define COR_LEVLREQ 0x40
51 #define COR_ENABLE_FUNC 0x01
53 #define PLX_PCIIPR 0x3d /* PCI Interrupt Pin */
55 #define PLX_INTCSR 0x4c /* Interrupt Control/Status Register */
57 #define PLX_CNTRL 0x50
64 PLXDEV(0x10b7, 0x7770, "3Com AirConnect PCI 777A"),
65 PLXDEV(0x111a, 0x1023, "Siemens SpeedStream SS1023"),
66 PLXDEV(0x126c, 0x8030, "Nortel emobility"),
67 PLXDEV(0x1562, 0x0001, "Symbol LA-4123"),
[all …]
/openbmc/linux/drivers/perf/
H A Dmarvell_cn10k_ddr_pmu.c17 #define DDRC_PERF_CNT_OP_MODE_CTRL 0x8020
18 #define OP_MODE_CTRL_VAL_MANNUAL 0x1
21 #define DDRC_PERF_CNT_START_OP_CTRL 0x8028
22 #define START_OP_CTRL_VAL_START 0x1ULL
23 #define START_OP_CTRL_VAL_ACTIVE 0x2
26 #define DDRC_PERF_CNT_END_OP_CTRL 0x8030
27 #define END_OP_CTRL_VAL_END 0x1ULL
30 #define DDRC_PERF_CNT_END_STATUS 0x8038
31 #define END_STATUS_VAL_END_TIMER_MODE_END 0x1
34 #define DDRC_PERF_CFG_BASE 0x8040
[all …]
/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b.dtsi19 #size-cells = <0>;
25 reg = <0x200>;
37 reg = <0x201>;
49 reg = <0x202>;
61 reg = <0x203>;
169 hwrom@0 {
170 reg = <0x0 0x200000>;
225 reg = <0xc8000000 0x8000>;
228 ranges = <0x0 0xc8000000 0x8000>;
232 reg = <0x400 0x20>;
[all …]
H A Dmeson8.dtsi21 #size-cells = <0>;
27 reg = <0x200>;
39 reg = <0x201>;
51 reg = <0x202>;
63 reg = <0x203>;
177 hwrom@0 {
178 reg = <0x0 0x200000>;
193 reg = <0x4f00000 0x100000>;
248 reg = <0xc8000000 0x8000>;
251 ranges = <0x0 0xc8000000 0x8000>;
[all …]
/openbmc/linux/Documentation/virt/kvm/
H A Dapi.rst148 You probably want to use 0 as machine type.
159 address used by the VM. The IPA_Bits is encoded in bits[7-0] of the
169 0 Implies default size, 40bits (for backward compatibility)
195 :Returns: 0 on success; -1 on error
209 __u32 indices[0];
237 :Returns: 0 if unsupported; 1 (or some other positive integer) if supported
242 Generally 0 means no and 1 means yes, but some extensions may report
285 The vcpu id is an integer in the range [0, max_vcpu_id).
329 :Returns: 0 on success, -1 on error
344 since the last call to this ioctl. Bit 0 is the first page in the
[all …]
/openbmc/linux/drivers/hwmon/pmbus/
H A Dltc2978.c33 #define LTC2978_MFR_VOUT_PEAK 0xdd
34 #define LTC2978_MFR_VIN_PEAK 0xde
35 #define LTC2978_MFR_TEMPERATURE_PEAK 0xdf
36 #define LTC2978_MFR_SPECIAL_ID 0xe7 /* Undocumented on LTC3882 */
37 #define LTC2978_MFR_COMMON 0xef
40 #define LTC2978_MFR_VOUT_MIN 0xfb
41 #define LTC2978_MFR_VIN_MIN 0xfc
42 #define LTC2978_MFR_TEMPERATURE_MIN 0xfd
45 #define LTC2974_MFR_IOUT_PEAK 0xd7
46 #define LTC2974_MFR_IOUT_MIN 0xd8
[all …]
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c28 #define CDV_LIMIT_SINGLE_LVDS_96 0
41 .m1 = {.min = 0, .max = 0},
53 .m1 = {.min = 0, .max = 0},
68 .m1 = {.min = 0, .max = 0},
80 .m1 = {.min = 0, .max = 0},
92 .m1 = {.min = 0, .max = 0},
104 .m1 = {.min = 0, .max = 0},
115 int ret__ = 0; \
134 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
144 SET_FIELD(0xf, SB_BYTE_ENABLE)); in cdv_sb_read()
[all …]
/openbmc/linux/drivers/net/ethernet/freescale/enetc/
H A Denetc_hw.h10 #define ENETC_DEV_ID_PF 0xe100
11 #define ENETC_DEV_ID_VF 0xef00
12 #define ENETC_DEV_ID_PTP 0xee02
15 #define ENETC_BAR_REGS 0
17 /** SI regs, offset: 0h */
18 #define ENETC_SIMR 0
20 #define ENETC_SIMR_RSSE BIT(0)
21 #define ENETC_SICTR0 0x18
22 #define ENETC_SICTR1 0x1c
23 #define ENETC_SIPCAPR0 0x20
[all …]

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