Home
last modified time | relevance | path

Searched +full:0 +full:x594 (Results 1 – 25 of 56) sorted by relevance

123

/openbmc/u-boot/drivers/clk/sunxi/
H A Dclk_a80.c16 [CLK_SPI0] = GATE(0x430, BIT(31)),
17 [CLK_SPI1] = GATE(0x434, BIT(31)),
18 [CLK_SPI2] = GATE(0x438, BIT(31)),
19 [CLK_SPI3] = GATE(0x43c, BIT(31)),
21 [CLK_BUS_MMC] = GATE(0x580, BIT(8)),
22 [CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
23 [CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
24 [CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
25 [CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
27 [CLK_BUS_UART0] = GATE(0x594, BIT(16)),
[all …]
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun9i-a80.c23 #define CCU_SUN9I_LOCK_REG 0x09c
32 #define SUN9I_A80_PLL_C0CPUX_REG 0x000
33 #define SUN9I_A80_PLL_C1CPUX_REG 0x004
37 .lock = BIT(0),
38 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
52 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
66 * and 24.576 MHz, ignore them for now. Enforce d1 = 0 and d2 = 0.
68 #define SUN9I_A80_PLL_AUDIO_REG 0x008
73 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
74 .m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0),
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h22 u32 reserved[0x1a];
25 u32 reserved2[0x18];
34 check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
50 u32 reserved6[0x0a];
52 u32 reserved7[0x14];
54 u32 reserved8[0x1d];
56 u32 reserved9[0x2b];
63 u32 reserved10[0x1a];
68 check_member(rk3399_cru, sdio1_con[1], 0x594);
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dqcom-qce.yaml145 reg = <0xfd45a000 0x6000>;
152 iommus = <&apps_smmu 0x584 0x0011>,
153 <&apps_smmu 0x586 0x0011>,
154 <&apps_smmu 0x594 0x0011>,
155 <&apps_smmu 0x596 0x0011>;
/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6dl-pinfunc.h17 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
20 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
21 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
22 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
24 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
25 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
26 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx6sl-pinfunc.h17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
18 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
20 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
23 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
24 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
25 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dboard_common.c33 #define PHY_RESET_MASK (BIT(GRP_F + 0) | BIT(GRP_F + 2)) in reset_eth_phy()
35 u32 value = readl(0x1e780020); in reset_eth_phy()
36 u32 direction = readl(0x1e780024); in reset_eth_phy()
42 writel(direction, 0x1e780024); in reset_eth_phy()
43 writel(value, 0x1e780020); in reset_eth_phy()
44 while((readl(0x1e780020) & PHY_RESET_MASK) != 0); in reset_eth_phy()
49 writel(value, 0x1e780020); in reset_eth_phy()
50 while((readl(0x1e780020) & PHY_RESET_MASK) != PHY_RESET_MASK); in reset_eth_phy()
66 if (rev_id == 0x0501030305010303 || rev_id == 0x0501020305010203) { in board_init()
68 tmp_val = readl(0x1e60008c) & (~BIT(0)); in board_init()
[all …]
/openbmc/linux/include/linux/mfd/mt6358/
H A Dregisters.h10 #define MT6358_SWCID 0xa
11 #define MT6358_TOPSTATUS 0x28
12 #define MT6358_TOP_RST_MISC 0x14c
13 #define MT6358_MISC_TOP_INT_CON0 0x188
14 #define MT6358_MISC_TOP_INT_STATUS0 0x194
15 #define MT6358_TOP_INT_STATUS0 0x19e
16 #define MT6358_SCK_TOP_INT_CON0 0x52e
17 #define MT6358_SCK_TOP_INT_STATUS0 0x53a
18 #define MT6358_EOSC_CALI_CON0 0x540
19 #define MT6358_EOSC_CALI_CON1 0x542
[all …]
/openbmc/u-boot/include/
H A Dtsi148.h14 #define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148
23 unsigned int otsau; /* 0x000 Outbound start upper */
24 unsigned int otsal; /* 0x004 Outbouud start lower */
25 unsigned int oteau; /* 0x008 Outbound end upper */
26 unsigned int oteal; /* 0x00c Outbound end lower */
27 unsigned int otofu; /* 0x010 Outbound translation upper */
28 unsigned int otofl; /* 0x014 Outbound translation lower */
29 unsigned int otbs; /* 0x018 Outbound translation 2eSST */
30 unsigned int otat; /* 0x01c Outbound translation attr */
34 unsigned int itsau; /* 0x000 inbound start upper */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dscu_ast2600.h17 u32 hwstrap; /* 0x500 */
18 u32 hwstrap_clr; /* 0x504 */
19 u32 hwstrap_protect; /* 0x508 */
23 u32 protection_key; /* 0x000 */
24 u32 chip_id0; /* 0x004 */
25 u32 reserve_0x08; /* 0x008 */
26 u32 reserve_0x0C; /* 0x00C */
27 u32 reserve_0x10; /* 0x010 */
28 u32 chip_id1; /* 0x014 */
29 u32 reserve_0x18; /* 0x018 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun9i.h12 u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */
13 u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */
14 u32 pll3_audio_cfg; /* 0x08 audio pll configuration */
15 u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */
16 u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */
17 u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */
18 u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */
19 u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */
20 u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */
21 u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */
[all …]
/openbmc/linux/include/linux/mfd/mt6359/
H A Dregisters.h10 #define MT6359_SWCID 0xa
11 #define MT6359_TOPSTATUS 0x2a
12 #define MT6359_TOP_RST_MISC 0x14c
13 #define MT6359_MISC_TOP_INT_CON0 0x188
14 #define MT6359_MISC_TOP_INT_STATUS0 0x194
15 #define MT6359_TOP_INT_STATUS0 0x19e
16 #define MT6359_SCK_TOP_INT_CON0 0x528
17 #define MT6359_SCK_TOP_INT_STATUS0 0x534
18 #define MT6359_EOSC_CALI_CON0 0x53a
19 #define MT6359_EOSC_CALI_CON1 0x53c
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Dr9a07g043-cpg.c60 {0, 1},
64 {0, 0},
68 {0, 1},
73 {0, 0},
88 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
135 0x514, 0),
137 0x518, 0),
139 0x518, 1),
143 0x518, 0),
145 0x518, 1),
[all …]
H A Dr9a07g044-cpg.c70 {0, 1},
74 {0, 0},
78 {0, 1},
83 {0, 0},
87 {0, 16},
91 {0, 0},
104 struct cpg_core_clk drp[0];
114 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
187 struct rzg2l_mod_clk drp[0];
192 0x514, 0),
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dpm-imx5.c26 #define MXC_CCM_CLPCR 0x54
27 #define MXC_CCM_CLPCR_LPM_OFFSET 0
28 #define MXC_CCM_CLPCR_LPM_MASK 0x3
30 #define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
31 #define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
33 #define MXC_CORTEXA8_PLAT_LPC 0xc
34 #define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
37 #define MXC_SRPG_NEON_SRPGCR 0x280
38 #define MXC_SRPG_ARM_SRPGCR 0x2a0
39 #define MXC_SRPG_EMPGC0_SRPGCR 0x2c0
[all …]
/openbmc/qemu/hw/net/fsl_etsec/
H A Dregisters.h49 #define DMACTRL_WOP (1 << 0)
51 #define IEVENT_PERR (1 << 0)
94 #define MACCFG1_TX_EN (1 << 0)
100 #define MIIMCOM_READ (1 << 0)
103 #define RCTRL_PRSDEP_MASK (0x3)
109 #define TSEC_ID (0x000 / 4)
110 #define TSEC_ID2 (0x004 / 4)
111 #define IEVENT (0x010 / 4)
112 #define IMASK (0x014 / 4)
113 #define EDIS (0x018 / 4)
[all …]
/openbmc/linux/drivers/media/pci/saa7134/
H A Dsaa7134-reg.h12 # define PCI_DEVICE_ID_PHILIPS_SAA7130 0x7130
15 # define PCI_DEVICE_ID_PHILIPS_SAA7133 0x7133
18 # define PCI_DEVICE_ID_PHILIPS_SAA7134 0x7134
21 # define PCI_DEVICE_ID_PHILIPS_SAA7135 0x7135
29 /* DMA channels, n = 0 ... 6 */
30 #define SAA7134_RS_BA1(n) ((0x200 >> 2) + 4*n)
31 #define SAA7134_RS_BA2(n) ((0x204 >> 2) + 4*n)
32 #define SAA7134_RS_PITCH(n) ((0x208 >> 2) + 4*n)
33 #define SAA7134_RS_CONTROL(n) ((0x20c >> 2) + 4*n)
34 #define SAA7134_RS_CONTROL_WSWAP (0x01 << 25)
[all …]
/openbmc/linux/sound/soc/sh/rcar/
H A Dgen.c52 RSND_REG_SET(id, offset, 0, #id)
68 return 0; in rsnd_is_accessible_reg()
90 return 0; in rsnd_mod_read()
173 memset(&regc, 0, sizeof(regc)); in _rsnd_gen_regmap_init()
198 for (i = 0; i < conf_size; i++) { in _rsnd_gen_regmap_init()
202 regf.lsb = 0; in _rsnd_gen_regmap_init()
215 return 0; in _rsnd_gen_regmap_init()
224 RSND_GEN_S_REG(SSI_SYS_INT_ENABLE0, 0x850), in rsnd_gen4_probe()
225 RSND_GEN_S_REG(SSI_SYS_INT_ENABLE2, 0x858), in rsnd_gen4_probe()
226 RSND_GEN_S_REG(SSI_SYS_INT_ENABLE4, 0x890), in rsnd_gen4_probe()
[all …]

123