| /openbmc/u-boot/arch/arm/mach-imx/mx5/ |
| H A D | soc.c | 25 int system_rev = 0x51000; in get_cpu_rev()
27 int system_rev = 0x53000; in get_cpu_rev()
33 case 0x02: in get_cpu_rev()
36 case 0x10: in get_cpu_rev()
37 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) in get_cpu_rev()
42 case 0x20: in get_cpu_rev()
50 if (reg < 0x20) in get_cpu_rev()
82 for (i = 0; i < 6; i++) in imx_get_mac_from_fuse()
83 mac[i] = readl(&fuse->mac_addr[i]) & 0xff; in imx_get_mac_from_fuse()
94 * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
[all …]
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| /openbmc/linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos54xx.dtsi | 42 <7 0>,
60 reg = <0x02020000 0x54000>;
63 ranges = <0 0x02020000 0x54000>;
65 smp-sram@0 {
67 reg = <0x0 0x1000>;
72 reg = <0x53000 0x1000>;
79 reg = <0x101c0000 0xb00>;
96 reg = <0x101d0000 0x100>;
102 reg = <0x12d10000 0x100>;
111 reg = <0x12ca0000 0x1000>;
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/sram/ |
| H A D | sram.yaml | 159 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
163 ranges = <0 0x5c000000 0x40000>;
166 reg = <0x100 0x50>;
170 reg = <0x1000 0x1000>;
175 reg = <0x20000 0x20000>;
190 reg = <0x02020000 0x54000>;
193 ranges = <0 0x02020000 0x54000>;
195 smp-sram@0 {
197 reg = <0x0 0x1000>;
202 reg = <0x53000 0x1000>;
[all …]
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| /openbmc/linux/drivers/virt/vboxguest/ |
| H A D | vmmdev.h | 17 #define VMMDEV_PORT_OFF_REQUEST 0
50 #define VMMDEV_EVENT_MOUSE_CAPABILITIES_CHANGED BIT(0)
72 #define VMMDEV_EVENT_VALID_EVENT_MASK 0x000007ffU
79 #define VMMDEV_VERSION 0x00010004
81 #define VMMDEV_VERSION_MINOR (VMMDEV_VERSION & 0xffff)
87 #define VMMDEV_REQUEST_HEADER_VERSION 0x10001
124 #define VMMDEV_MOUSE_GUEST_CAN_ABSOLUTE BIT(0)
155 #define VMMDEV_MOUSE_RANGE_MIN 0
157 #define VMMDEV_MOUSE_RANGE_MAX 0xFFFF
181 #define VMMDEV_HVF_HGCM_PHYS_PAGE_LIST BIT(0)
[all …]
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| /openbmc/linux/drivers/soc/tegra/cbb/ |
| H A D | tegra234-cbb.c | 8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_MN_MASTER_ERR_EN_0 0x200
34 #define FABRIC_MN_MASTER_ERR_FORCE_0 0x204
35 #define FABRIC_MN_MASTER_ERR_STATUS_0 0x208
36 #define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0 0x20c
[all …]
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| /openbmc/linux/drivers/infiniband/hw/qib/ |
| H A D | qib_7220_regs.h | 37 #define QIB_7220_Revision_OFFS 0x0
38 #define QIB_7220_Revision_R_Simulator_LSB 0x3F
39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7220_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
42 #define QIB_7220_Revision_R_Emulation_Revcode_LSB 0x28
43 #define QIB_7220_Revision_R_Emulation_Revcode_RMASK 0x3FFFFF
44 #define QIB_7220_Revision_BoardID_LSB 0x20
45 #define QIB_7220_Revision_BoardID_RMASK 0xFF
46 #define QIB_7220_Revision_R_SW_LSB 0x18
[all …]
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap5-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
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| H A D | dra7-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x4a000000 */
21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/umc/ |
| H A D | umc_6_7_0_offset.h | 29 // base address: 0x50f00
30 …MCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
31 …e regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
32 …MCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
33 …e regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0
34 …MCA_UMC_UMC0_MCUMC_MISC0T0 0x03c6
35 …e regMCA_UMC_UMC0_MCUMC_MISC0T0_BASE_IDX 0
36 …MCA_UMC_UMC0_MCUMC_IPIDT0 0x03ca
37 …e regMCA_UMC_UMC0_MCUMC_IPIDT0_BASE_IDX 0
38 …MCA_UMC_UMC0_MCUMC_SYNDT0 0x03cc
[all …]
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| /openbmc/linux/drivers/clk/qcom/ |
| H A D | gcc-msm8909.c | 52 { P_XO, 0 },
64 .offset = 0x21000,
67 .enable_reg = 0x45000,
68 .enable_mask = BIT(0),
80 .offset = 0x21000,
94 .l_reg = 0x20004,
95 .m_reg = 0x20008,
96 .n_reg = 0x2000c,
97 .config_reg = 0x20010,
98 .mode_reg = 0x20000,
[all …]
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| H A D | gcc-sdx75.c | 67 .offset = 0x0,
70 .enable_reg = 0x7d000,
71 .enable_mask = BIT(0),
84 { 0x1, 2 },
89 .offset = 0x0,
106 .offset = 0x4000,
109 .enable_reg = 0x7d000,
123 .offset = 0x5000,
126 .enable_reg = 0x7d000,
140 .offset = 0x6000,
[all …]
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| H A D | gcc-msm8917.c | 54 .offset = 0x21000,
57 .enable_reg = 0x45008,
72 .offset = 0x21000,
75 .enable_reg = 0x45000,
76 .enable_mask = BIT(0),
89 .offset = 0x21000,
102 { 700000000, 1400000000, 0 },
107 .config_ctl_val = 0x4001055b,
108 .early_output_mask = 0,
114 .offset = 0x22000,
[all …]
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| H A D | gcc-msm8916.c | 45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
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| H A D | gcc-sm6375.c | 54 { 249600000, 2000000000, 0 },
58 { 595200000, 3600000000UL, 0 },
62 .offset = 0x0,
65 .enable_reg = 0x79000,
66 .enable_mask = BIT(0),
79 { 0x1, 2 },
84 .offset = 0x0,
101 { 0x3, 3 },
106 .offset = 0x0,
123 .offset = 0x1000,
[all …]
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| H A D | gcc-msm8976.c | 56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
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| H A D | gcc-msm8939.c | 53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
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| H A D | gcc-msm8953.c | 40 .offset = 0x21000,
43 .enable_reg = 0x45000,
44 .enable_mask = BIT(0),
70 .offset = 0x21000,
83 .offset = 0x4a000,
86 .enable_reg = 0x45000,
100 .offset = 0x4a000,
113 { 1000000000, 2000000000, 0 },
118 .config_ctl_val = 0x4001055b,
119 .early_output_mask = 0,
[all …]
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