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/openbmc/u-boot/board/sunxi/
H A DREADME.nand35 sunxi-fel write 0x4a000000 u-boot-dtb.bin
36 sunxi-fel write 0x43000000 spl/sunxi-spl-with-ecc.bin
39 sunxi-fel exe 0x4a000000
48 nand write.raw.noverify 0x43000000 0 40
49 nand write.raw.noverify 0x43000000 0x400000 40
52 nand write 0x4a000000 0x800000 0xc0000
H A Dmksunxi_fit_atf.sh6 # usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
17 BL31_ADDR=0x104000
19 BL31_ADDR=0x44000
36 load = <0x4a000000>;
/openbmc/linux/arch/arm/mach-omap2/
H A Domap54xx.h17 #define L4_54XX_BASE 0x4a000000
18 #define L4_WK_54XX_BASE 0x4ae00000
19 #define L4_PER_54XX_BASE 0x48000000
20 #define L3_54XX_BASE 0x44000000
21 #define OMAP54XX_32KSYNCT_BASE 0x4ae04000
22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
23 #define OMAP54XX_CM_CORE_BASE 0x4a008000
24 #define OMAP54XX_PRM_BASE 0x4ae06000
25 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
26 #define OMAP54XX_SCM_BASE 0x4a002000
[all …]
H A Domap44xx.h17 #define L4_44XX_BASE 0x4a000000
18 #define L4_WK_44XX_BASE 0x4a300000
19 #define L4_PER_44XX_BASE 0x48000000
20 #define L4_EMU_44XX_BASE 0x54000000
21 #define L3_44XX_BASE 0x44000000
22 #define OMAP44XX_EMIF1_BASE 0x4c000000
23 #define OMAP44XX_EMIF2_BASE 0x4d000000
24 #define OMAP44XX_DMM_BASE 0x4e000000
25 #define OMAP4430_32KSYNCT_BASE 0x4a304000
26 #define OMAP4430_CM1_BASE 0x4a004000
[all …]
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/openbmc/u-boot/configs/
H A Dadp-ae3xx_defconfig2 CONFIG_SYS_TEXT_BASE=0x4A000000
/openbmc/linux/arch/arm/mach-pxa/
H A Daddr-map.h8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]
H A Dsmemc.h11 #define PXA2XX_SMEMC_BASE 0x48000000
12 #define PXA3XX_SMEMC_BASE 0x4a000000
13 #define SMEMC_VIRT IOMEM(0xf6000000)
15 #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
16 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
17 #define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */
18 #define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */
19 #define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */
20 #define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
21 #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
[all …]
/openbmc/u-boot/doc/uImage.FIT/
H A Dmulti_spl.its19 #address-cells = <0x1>;
28 load = <0x4a000000>;
36 load = <0x18000>;
37 entry = <0x18000>;
45 load = <0x40000>;
52 load = <0x4fa00000>;
60 load = <0x4fa00000>;
68 load = <0x40080000>;
76 load = <0x4fe00000>;
/openbmc/u-boot/arch/arm/include/asm/arch-omap4/
H A Domap.h26 #define OMAP44XX_L4_CORE_BASE 0x4A000000
27 #define OMAP44XX_L4_WKUP_BASE 0x4A300000
28 #define OMAP44XX_L4_PER_BASE 0x48000000
30 #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
31 #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
36 #define CONTROL_ID_CODE 0x4A002204
38 #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
39 #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
40 #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
41 #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
[all …]
/openbmc/linux/arch/powerpc/lib/
H A Dtest-code-patching.c17 return 0; in instr_is_branch_to_addr()
28 } while (0)
39 check(instr_is_branch_iform(ppc_inst(0x48000000))); in test_branch_iform()
41 check(instr_is_branch_iform(ppc_inst(0x4bffffff))); in test_branch_iform()
43 check(!instr_is_branch_iform(ppc_inst(0xcbffffff))); in test_branch_iform()
45 check(!instr_is_branch_iform(ppc_inst(0x7bffffff))); in test_branch_iform()
48 check(instr_is_branch_iform(ppc_inst(0x48000001))); in test_branch_iform()
50 check(instr_is_branch_iform(ppc_inst(0x4bfffffd))); in test_branch_iform()
52 check(instr_is_branch_iform(ppc_inst(0x4bff00fd))); in test_branch_iform()
54 check(!instr_is_branch_iform(ppc_inst(0x7bfffffd))); in test_branch_iform()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Domap.h23 #define OMAP54XX_L4_CORE_BASE 0x4A000000
24 #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
25 #define OMAP54XX_L4_PER_BASE 0x48000000
28 #define CONTROL_CORE_ID_CODE 0x4A002204
29 #define CONTROL_WKUP_ID_CODE 0x4AE0C204
38 #define DRA7_USB_OTG_SS1_BASE 0x48890000
39 #define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000
40 #define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00
41 #define DRA7_USB3_PHY1_POWER 0x4A002370
42 #define DRA7_USB2_PHY1_POWER 0x4A002300
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0_3.c31 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000),
32 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000),
33 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000),
34 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000),
35 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS, 0x003f3fff, 0xe0000000),
36 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000),
37 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000),
38 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000),
39 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE0, 0x00040000, 0xe0000000),
40 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE1, 0x00000000, 0xe0000000),
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3.yaml188 - 0 # -6dB de-emphasis
264 quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
299 minimum: 0
300 maximum: 0x3f
393 port@0:
417 reg = <0x4a030000 0xcfff>;
418 interrupts = <0 92 4>;
425 reg = <0x4a000000 0xcfff>;
426 interrupts = <0 92 4>;
/openbmc/u-boot/include/configs/
H A Dsunxi-common.h24 # define CONFIG_MACH_TYPE_COMPAT_REV 0
62 #define SDRAM_OFFSET(x) 0x2##x
63 #define CONFIG_SYS_SDRAM_BASE 0x20000000
64 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */
68 #define CONFIG_SPL_STACK_R_ADDR 0x2fe00000
69 #define CONFIG_SPL_BSS_START_ADDR 0x2ff80000
71 #define SDRAM_OFFSET(x) 0x4##x
72 #define CONFIG_SYS_SDRAM_BASE 0x40000000
73 #define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */
74 /* V3s do not have enough memory to place code at 0x4a000000 */
[all …]
/openbmc/u-boot/
H A DKconfig139 default 0x1000 if AM33XX
140 default 0x2800 if SANDBOX
141 default 0x400
271 default 0x0
328 default 0x10000000
508 default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
509 default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
510 default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
511 default 0x42e00000 if ARCH_SUNXI && MACH_SUN8I_V3S
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam33xx-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
H A Domap4-l4.dtsi2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
H A Dam437x-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
H A Ddm814x.dtsi31 #size-cells = <0>;
32 cpu@0 {
35 reg = <0>;
65 reg = <0x47400000 0x1000>;
73 reg = <0x47401300 0x100>;
76 #phy-cells = <0>;
81 reg = <0x47401400 0x400
82 0x47401000 0x200>;
94 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
95 &cppi41dma 2 0 &cppi41dma 3 0
[all …]
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/openbmc/linux/arch/arm64/include/asm/
H A Dinsn.h18 AARCH64_INSN_HINT_NOP = 0x0 << 5,
19 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
20 AARCH64_INSN_HINT_WFE = 0x2 << 5,
21 AARCH64_INSN_HINT_WFI = 0x3 << 5,
22 AARCH64_INSN_HINT_SEV = 0x4 << 5,
23 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
25 AARCH64_INSN_HINT_XPACLRI = 0x07 << 5,
26 AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
27 AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
28 AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
[all …]
/openbmc/qemu/hw/arm/
H A Dvexpress.c50 #define VEXPRESS_BOARD_ID 0x8e0
54 /* Number of virtio transports to create (0..8; limited by
98 [VE_NORFLASHALIAS] = 0,
99 /* CS7: 0x10000000 .. 0x10020000 */
100 [VE_SYSREGS] = 0x10000000,
101 [VE_SP810] = 0x10001000,
102 [VE_SERIALPCI] = 0x10002000,
103 [VE_PL041] = 0x10004000,
104 [VE_MMCI] = 0x10005000,
105 [VE_KMI0] = 0x10006000,
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]

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