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/openbmc/linux/drivers/remoteproc/
H A Dmtk_common.h15 #define MT8183_SW_RSTN 0x0
16 #define MT8183_SW_RSTN_BIT BIT(0)
17 #define MT8183_SCP_TO_HOST 0x1C
18 #define MT8183_SCP_IPC_INT_BIT BIT(0)
20 #define MT8183_HOST_TO_SCP 0x28
21 #define MT8183_HOST_IPC_INT_BIT BIT(0)
22 #define MT8183_WDT_CFG 0x84
23 #define MT8183_SCP_CLK_SW_SEL 0x4000
24 #define MT8183_SCP_CLK_DIV_SEL 0x4024
25 #define MT8183_SCP_SRAM_PDN 0x402C
[all …]
/openbmc/linux/drivers/gpu/host1x/hw/
H A Dhw_host1x08_common.h6 #define HOST1X_COMMON_OFA_MLOCK 0x4050
7 #define HOST1X_COMMON_NVJPG1_MLOCK 0x4070
8 #define HOST1X_COMMON_VIC_MLOCK 0x4078
9 #define HOST1X_COMMON_NVENC_MLOCK 0x407c
10 #define HOST1X_COMMON_NVDEC_MLOCK 0x4080
11 #define HOST1X_COMMON_NVJPG_MLOCK 0x4084
/openbmc/u-boot/drivers/mmc/
H A Dmv_sdhci.c11 #define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4))
12 #define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4))
21 for (i = 0; i < 4; i++) { in sdhci_mvebu_mbus_config()
22 writel(0, base + SDHCI_WINDOW_CTRL(i)); in sdhci_mvebu_mbus_config()
23 writel(0, base + SDHCI_WINDOW_BASE(i)); in sdhci_mvebu_mbus_config()
26 for (i = 0; i < dram->num_cs; i++) { in sdhci_mvebu_mbus_config()
30 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | in sdhci_mvebu_mbus_config()
43 #define SD_CE_ATA_2 0xEA
44 #define MMC_CARD 0x1000
45 #define MMC_WIDTH 0x0100
[all …]
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-c3.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0x0 0x0>;
25 reg = <0x0 0x1>;
47 #clock-cells = <0>;
68 #address-cells = <0>;
70 reg = <0x0 0xfff01000 0 0x1000>,
71 <0x0 0xfff02000 0 0x2000>,
72 <0x0 0xfff04000 0 0x2000>,
73 <0x0 0xfff06000 0 0x2000>;
[all …]
H A Dmeson-s4.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0x0 0x0>;
25 reg = <0x0 0x1>;
32 reg = <0x0 0x2>;
39 reg = <0x0 0x3>;
61 #clock-cells = <0>;
84 #address-cells = <0>;
86 reg = <0x0 0xfff01000 0 0x1000>,
87 <0x0 0xfff02000 0 0x2000>,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dti,j721e-system-controller.yaml48 "^mux-controller@[0-9a-f]+$":
53 "^clock-controller@[0-9a-f]+$":
59 "phy@[0-9a-f]+$":
65 "^chipid@[0-9a-f]+$":
84 reg = <0x00100000 0x1c000>;
91 reg = <0x00004080 0x50>;
95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
[all …]
/openbmc/linux/drivers/ntb/hw/intel/
H A Dntb_hw_gen3.h50 #define GEN3_IMBAR1SZ_OFFSET 0x00d0
51 #define GEN3_IMBAR2SZ_OFFSET 0x00d1
52 #define GEN3_EMBAR1SZ_OFFSET 0x00d2
53 #define GEN3_EMBAR2SZ_OFFSET 0x00d3
54 #define GEN3_DEVCTRL_OFFSET 0x0098
55 #define GEN3_DEVSTS_OFFSET 0x009a
56 #define GEN3_UNCERRSTS_OFFSET 0x014c
57 #define GEN3_CORERRSTS_OFFSET 0x0158
58 #define GEN3_LINK_STATUS_OFFSET 0x01a2
60 #define GEN3_NTBCNTL_OFFSET 0x0000
[all …]
/openbmc/linux/drivers/dma/xilinx/
H A Dxdma-regs.h32 #define XDMA_DESC_MAGIC 0xad4bUL
34 #define XDMA_DESC_FLAGS_BITS GENMASK(7, 0)
35 #define XDMA_DESC_STOPPED BIT(0)
72 #define XDMA_CHAN_IDENTIFIER 0x0
73 #define XDMA_CHAN_CONTROL 0x4
74 #define XDMA_CHAN_CONTROL_W1S 0x8
75 #define XDMA_CHAN_CONTROL_W1C 0xc
76 #define XDMA_CHAN_STATUS 0x40
77 #define XDMA_CHAN_COMPLETED_DESC 0x48
78 #define XDMA_CHAN_ALIGNMENTS 0x4c
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Drv5151 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dspu.h23 #define MFC_PUT_CMD 0x20
24 #define MFC_PUTS_CMD 0x28
25 #define MFC_PUTR_CMD 0x30
26 #define MFC_PUTF_CMD 0x22
27 #define MFC_PUTB_CMD 0x21
28 #define MFC_PUTFS_CMD 0x2A
29 #define MFC_PUTBS_CMD 0x29
30 #define MFC_PUTRF_CMD 0x32
31 #define MFC_PUTRB_CMD 0x31
32 #define MFC_PUTL_CMD 0x24
[all …]
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_pci_id_tbl.h46 * -- The PCI Function Number to use in the PCI Device ID Table. "0"
73 /* T4 and later ASICs use a PCI Device ID scheme of 0xVFPP where:
76 * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
97 CH_PCI_ID_TABLE_FENTRY(0x4000), /* T440-dbg */
98 CH_PCI_ID_TABLE_FENTRY(0x4001), /* T420-cr */
99 CH_PCI_ID_TABLE_FENTRY(0x4002), /* T422-cr */
100 CH_PCI_ID_TABLE_FENTRY(0x4003), /* T440-cr */
101 CH_PCI_ID_TABLE_FENTRY(0x4004), /* T420-bch */
102 CH_PCI_ID_TABLE_FENTRY(0x4005), /* T440-bch */
103 CH_PCI_ID_TABLE_FENTRY(0x4006), /* T440-ch */
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dplatform.S15 * +----------------------+ 0x40
17 * +----------------------+ 0x3c
22 * +----------------------+ 0x10
24 * +----------------------+ 0x0c
26 * +----------------------+ 0x08
28 * +----------------------+ 0x04
33 #define SCU_BASE 0x1e6e2000
35 #define SCU_PROT_KEY2 (SCU_BASE + 0x010)
36 #define SCU_REV_ID (SCU_BASE + 0x014)
37 #define SCU_SYSRST_CTRL (SCU_BASE + 0x040)
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/openbmc/linux/include/linux/mfd/wm831x/
H A Dcore.h25 #define WM831X_RESET_ID 0x00
26 #define WM831X_REVISION 0x01
27 #define WM831X_PARENT_ID 0x4000
28 #define WM831X_SYSVDD_CONTROL 0x4001
29 #define WM831X_THERMAL_MONITORING 0x4002
30 #define WM831X_POWER_STATE 0x4003
31 #define WM831X_WATCHDOG 0x4004
32 #define WM831X_ON_PIN_CONTROL 0x4005
33 #define WM831X_RESET_CONTROL 0x4006
34 #define WM831X_CONTROL_INTERFACE 0x4007
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dadau1781.c24 #define ADAU1781_DMIC_BEEP_CTRL 0x4008
25 #define ADAU1781_LEFT_PGA 0x400e
26 #define ADAU1781_RIGHT_PGA 0x400f
27 #define ADAU1781_LEFT_PLAYBACK_MIXER 0x401c
28 #define ADAU1781_RIGHT_PLAYBACK_MIXER 0x401e
29 #define ADAU1781_MONO_PLAYBACK_MIXER 0x401f
30 #define ADAU1781_LEFT_LINEOUT 0x4025
31 #define ADAU1781_RIGHT_LINEOUT 0x4026
32 #define ADAU1781_SPEAKER 0x4027
33 #define ADAU1781_BEEP_ZC 0x4028
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dhpfb.c34 #define TC_NBLANK 0x4080
35 #define TC_WEN 0x4088
36 #define TC_REN 0x408c
37 #define TC_FBEN 0x4090
38 #define TC_PRR 0x40ea
41 #define RR_CLEAR 0x0
42 #define RR_COPY 0x3
43 #define RR_NOOP 0x5
44 #define RR_XOR 0x6
45 #define RR_INVERT 0xa
[all …]
H A Dgxt4500.c19 #define PCI_DEVICE_ID_IBM_GXT4500P 0x21c
20 #define PCI_DEVICE_ID_IBM_GXT6500P 0x21b
21 #define PCI_DEVICE_ID_IBM_GXT4000P 0x16e
22 #define PCI_DEVICE_ID_IBM_GXT6000P 0x170
27 #define CFG_ENDIAN0 0x40
30 #define STATUS 0x1000
31 #define CTRL_REG0 0x1004
32 #define CR0_HALT_DMA 0x4
33 #define CR0_RASTER_RESET 0x8
34 #define CR0_GEOM_RESET 0x10
[all …]
/openbmc/linux/arch/alpha/include/asm/
H A Dcore_mcpcia.h58 * 00 00 Byte 1110 0x000
59 * 01 00 Byte 1101 0x020
60 * 10 00 Byte 1011 0x040
61 * 11 00 Byte 0111 0x060
63 * 00 01 Word 1100 0x008
64 * 01 01 Word 1001 0x028 <= Not supported in this code.
65 * 10 01 Word 0011 0x048
67 * 00 10 Tribyte 1000 0x010
68 * 01 10 Tribyte 0001 0x030
70 * 10 11 Longword 0000 0x058
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/westmereep-dp/
H A Dmemory.json4 "EventCode": "0x5",
7 "UMask": "0x2"
11 "EventCode": "0xB7, 0xBB",
13 "MSRIndex": "0x1a6,0x1a7",
14 "MSRValue": "0x3011",
16 "UMask": "0x1"
20 "EventCode": "0xB7, 0xBB",
22 "MSRIndex": "0x1a6,0x1a7",
23 "MSRValue": "0xf811",
25 "UMask": "0x1"
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/westmereep-sp/
H A Dmemory.json4 "EventCode": "0xB7, 0xBB",
6 "MSRIndex": "0x1a6,0x1a7",
7 "MSRValue": "0x6011",
9 "UMask": "0x1"
13 "EventCode": "0xB7, 0xBB",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0xF811",
18 "UMask": "0x1"
22 "EventCode": "0xB7, 0xBB",
24 "MSRIndex": "0x1a6,0x1a7",
[all …]
/openbmc/linux/drivers/net/ethernet/tehuti/
H A Dtehuti.h81 # define L32_64(x) (u32) ((u64)(x) & 0xffffffff)
83 # define H32_64(x) 0
105 # define NETDEV_TX_OK 0
134 #define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0)
189 * if len == 0 addr is dma
190 * if len != 0 addr is skb */
207 u64 InUCast; /* 0x7200 */
208 u64 InMCast; /* 0x7210 */
209 u64 InBCast; /* 0x7220 */
210 u64 InPkts; /* 0x7230 */
[all …]
/openbmc/linux/drivers/net/ethernet/agere/
H A Det131x.h53 #define LBCIF_DWORD0_GROUP 0xAC
54 #define LBCIF_DWORD1_GROUP 0xB0
57 #define LBCIF_ADDRESS_REGISTER 0xAC
58 #define LBCIF_DATA_REGISTER 0xB0
59 #define LBCIF_CONTROL_REGISTER 0xB1
60 #define LBCIF_STATUS_REGISTER 0xB2
63 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
64 #define LBCIF_CONTROL_PAGE_WRITE 0x02
65 #define LBCIF_CONTROL_EEPROM_RELOAD 0x08
66 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
[all …]
/openbmc/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_misc.c12 HNS_OP_RESET_FUNC = 0x1,
13 HNS_OP_SERDES_LP_FUNC = 0x2,
14 HNS_OP_LED_SET_FUNC = 0x3,
15 HNS_OP_GET_PORT_TYPE_FUNC = 0x4,
16 HNS_OP_GET_SFP_STAT_FUNC = 0x5,
17 HNS_OP_LOCATE_LED_SET_FUNC = 0x6,
21 HNS_DSAF_RESET_FUNC = 0x1,
22 HNS_PPE_RESET_FUNC = 0x2,
23 HNS_XGE_RESET_FUNC = 0x4,
24 HNS_GE_RESET_FUNC = 0x5,
[all …]
/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_dbg.c13 * | Module Init and Probe | 0x0199 | |
14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff |
15 * | Device Discovery | 0x2134 | 0x2112-0x2115 |
16 * | | | 0x2127-0x2128 |
17 * | Queue Command and IO tracing | 0x3074 | 0x300b |
18 * | | | 0x3027-0x3028 |
19 * | | | 0x303d-0x3041 |
20 * | | | 0x302e,0x3033 |
21 * | | | 0x3036,0x3038 |
22 * | | | 0x303a |
[all …]
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddrphy_csr.c11 { 0x200b2, 0x0 },
12 { 0x1200b2, 0x0 },
13 { 0x2200b2, 0x0 },
14 { 0x200cb, 0x0 },
15 { 0x10043, 0x0 },
16 { 0x110043, 0x0 },
17 { 0x210043, 0x0 },
18 { 0x10143, 0x0 },
19 { 0x110143, 0x0 },
20 { 0x210143, 0x0 },
[all …]

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