| /openbmc/linux/tools/testing/selftests/powerpc/pmu/ebb/ |
| H A D | busy_loop.S | 31 li r3, 0x3030
33 li r4, 0x4040
35 li r5, 0x5050
37 li r6, 0x6060
39 li r7, 0x7070
41 li r8, 0x0808
43 li r9, 0x0909
45 li r10, 0x1010
47 li r11, 0x1111
49 li r14, 0x1414
[all …]
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| /openbmc/linux/drivers/net/wireless/ath/ath11k/ |
| H A D | pci.h | 13 #define PCIE_SOC_GLOBAL_RESET 0x3008
16 #define WLAON_WARM_SW_ENTRY 0x1f80504
17 #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c
19 #define PCIE_Q6_COOKIE_ADDR 0x01f80500
20 #define PCIE_Q6_COOKIE_DATA 0xc0000000
23 #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040
26 #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004
28 #define PCIE_PCIE_PARF_LTSSM 0x1e081b0
29 #define PARM_LTSSM_VALUE 0x111
31 #define GCC_GCC_PCIE_HOT_RST 0x1e402bc
[all …]
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | mcp77.c | 45 return nvkm_rd32(device, 0x004600); in read_div()
52 u32 ctrl = nvkm_rd32(device, base + 0); in read_pll()
55 u32 post_div = 0; in read_pll()
56 u32 clock = 0; in read_pll()
60 case 0x4020: in read_pll()
61 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); in read_pll()
63 case 0x4028: in read_pll()
64 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; in read_pll()
70 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
71 M1 = (coef & 0x000000ff); in read_pll()
[all …]
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| /openbmc/u-boot/drivers/video/meson/ |
| H A D | meson_venc.c | 13 MESON_VENC_MODE_NONE = 0,
20 MESON_VENC_SOURCE_NONE = 0,
25 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
26 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
59 .video_prog_mode = 0xff,
60 .video_mode = 0x13,
61 .sch_adjust = 0x28,
62 .yc_delay = 0x343,
70 .video_contrast = 0,
71 .video_brightness = 0,
[all …]
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| /openbmc/linux/drivers/gpu/drm/meson/ |
| H A D | meson_venc.c | 64 #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
65 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
66 #define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbb offset in data sheet */
67 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
68 #define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbc offset in data sheet */
69 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
78 .video_prog_mode = 0xff,
79 .video_mode = 0x13,
80 .sch_adjust = 0x28,
81 .yc_delay = 0x343,
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | qcom,qcs404-pas.yaml | 69 reg = <0x0c700000 0x4040>;
75 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
84 qcom,smem-states = <&adsp_smp2p_out 0>;
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| H A D | qcom,sdx55-pas.yaml | 80 reg = <0x04080000 0x4040>;
86 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
99 qcom,smem-states = <&modem_smp2p_out 0>;
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| H A D | qcom,sc7180-pas.yaml | 103 reg = <0x04080000 0x4040>;
109 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
125 qcom,smem-states = <&modem_smp2p_out 0>;
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| H A D | qcom,qcs404-cdsp-pil.yaml | 122 reg = <0x00b00000 0x4040>;
125 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
154 qcom,halt-regs = <&tcsr 0x19004>;
158 qcom,smem-states = <&cdsp_smp2p_out 0>;
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| H A D | qcom,sm8150-pas.yaml | 143 reg = <0x17300000 0x4040>;
151 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
163 qcom,smem-states = <&adsp_smp2p_out 0>;
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| /openbmc/linux/drivers/media/rc/keymaps/ |
| H A D | rc-ct-90405.c | 5 * Copyright (C) 2021 Alexander Voronov <avv.0@ya.ru>
12 { 0x4014, KEY_SWITCHVIDEOMODE },
13 { 0x4012, KEY_POWER },
14 { 0x4044, KEY_TV },
15 { 0x40be43, KEY_3D_MODE },
16 { 0x400c, KEY_SUBTITLE },
17 { 0x4001, KEY_NUMERIC_1 },
18 { 0x4002, KEY_NUMERIC_2 },
19 { 0x4003, KEY_NUMERIC_3 },
20 { 0x4004, KEY_NUMERIC_4 },
[all …]
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| /openbmc/linux/arch/parisc/include/uapi/asm/ |
| H A D | socket.h | 9 #define SOL_SOCKET 0xffff
11 #define SO_DEBUG 0x0001
12 #define SO_REUSEADDR 0x0004
13 #define SO_KEEPALIVE 0x0008
14 #define SO_DONTROUTE 0x0010
15 #define SO_BROADCAST 0x0020
16 #define SO_LINGER 0x0080
17 #define SO_OOBINLINE 0x0100
18 #define SO_REUSEPORT 0x0200
19 #define SO_SNDBUF 0x1001
[all …]
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| /openbmc/linux/drivers/net/wireless/ath/ath12k/ |
| H A D | pci.h | 13 #define PCIE_SOC_GLOBAL_RESET 0x3008
16 #define WLAON_WARM_SW_ENTRY 0x1f80504
17 #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c
19 #define PCIE_Q6_COOKIE_ADDR 0x01f80500
20 #define PCIE_Q6_COOKIE_DATA 0xc0000000
23 #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040
26 #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004
28 #define PCIE_PCIE_PARF_LTSSM 0x1e081b0
29 #define PARM_LTSSM_VALUE 0x111
31 #define GCC_GCC_PCIE_HOT_RST 0x1e38338
[all …]
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| /openbmc/linux/drivers/ntb/hw/intel/ |
| H A D | ntb_hw_gen3.h | 50 #define GEN3_IMBAR1SZ_OFFSET 0x00d0
51 #define GEN3_IMBAR2SZ_OFFSET 0x00d1
52 #define GEN3_EMBAR1SZ_OFFSET 0x00d2
53 #define GEN3_EMBAR2SZ_OFFSET 0x00d3
54 #define GEN3_DEVCTRL_OFFSET 0x0098
55 #define GEN3_DEVSTS_OFFSET 0x009a
56 #define GEN3_UNCERRSTS_OFFSET 0x014c
57 #define GEN3_CORERRSTS_OFFSET 0x0158
58 #define GEN3_LINK_STATUS_OFFSET 0x01a2
60 #define GEN3_NTBCNTL_OFFSET 0x0000
[all …]
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| /openbmc/u-boot/fs/ext4/ |
| H A D | crc16.c | 13 /** CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1) */
15 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
16 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
17 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
18 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
19 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
20 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
21 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
22 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
23 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
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| /openbmc/linux/lib/ |
| H A D | crc16.c | 10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
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| /openbmc/u-boot/fs/ubifs/ |
| H A D | crc16.c | 11 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
13 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
14 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
15 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
16 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
17 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
18 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
19 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
20 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
21 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
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| /openbmc/u-boot/cmd/aspeed/ |
| H A D | peci.c | 6 #define AST_SCU (0x1e6e2000)
8 #define AST_SCU_SYSRST_CTRL (AST_SCU + 0x04)
10 #define AST_SCU_SYSRST_CLR2 (AST_SCU + 0x54)
13 #define AST_PECI (0x1e78b000)
14 #define AST_PECI_CTRL (AST_PECI + 0x00)
15 #define AST_PECI_TIMING (AST_PECI + 0x04)
16 #define AST_PECI_CMD (AST_PECI + 0x08)
17 #define AST_PECI_RW_LEN (AST_PECI + 0x0C)
18 #define AST_PECI_EXP_FCS (AST_PECI + 0x10)
19 #define AST_PECI_CAP_FCS (AST_PECI + 0x14)
[all …]
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| /openbmc/linux/drivers/watchdog/ |
| H A D | pika_wdt.c | 40 module_param(heartbeat, int, 0);
45 module_param(nowayout, bool, 0);
71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset()
80 unsigned reset = in_be32(pikawdt_private.fpga + 0x14); in pikawdt_reset()
83 out_be32(pikawdt_private.fpga + 0x14, reset); in pikawdt_reset()
117 if (test_and_set_bit(0, &pikawdt_private.open)) in pikawdt_open()
134 clear_bit(0, &pikawdt_private.open); in pikawdt_release()
135 pikawdt_private.expect_close = 0; in pikawdt_release()
136 return 0; in pikawdt_release()
146 return 0; in pikawdt_write()
[all …]
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| /openbmc/u-boot/board/freescale/imx8mq_evk/ |
| H A D | lpddr4_timing_b0.c | 16 { DDRC_DBG1(0), 0x00000001 },
18 { DDRC_PWRCTL(0), 0x00000001 },
19 { DDRC_MSTR(0), 0xa3080020 },
20 { DDRC_MSTR2(0), 0x00000000 },
21 { DDRC_RFSHTMG(0), 0x006100E0 },
22 { DDRC_INIT0(0), 0xC003061B },
23 { DDRC_INIT1(0), 0x009D0000 },
24 { DDRC_INIT3(0), 0x00D4002D },
26 { DDRC_INIT4(0), 0x00330008 },
28 { DDRC_INIT4(0), 0x00310008 },
[all …]
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| H A D | lpddr4_timing.c | 15 { DDRC_DBG1(0), 0x00000001 },
16 { DDRC_PWRCTL(0), 0x00000001 },
17 { DDRC_MSTR(0), 0xa3080020 },
18 { DDRC_MSTR2(0), 0x00000000 },
19 { DDRC_RFSHTMG(0), 0x006100E0 },
20 { DDRC_INIT0(0), 0xC003061B },
21 { DDRC_INIT1(0), 0x009D0000 },
22 { DDRC_INIT3(0), 0x00D4002D },
24 { DDRC_INIT4(0), 0x00330008 },
26 { DDRC_INIT4(0), 0x00310008 },
[all …]
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| /openbmc/linux/drivers/net/fddi/skfp/h/ |
| H A D | smt_p.h | 19 #define SMT_P0012 0x0012
21 #define SMT_P0015 0x0015
22 #define SMT_P0016 0x0016
23 #define SMT_P0017 0x0017
24 #define SMT_P0018 0x0018
25 #define SMT_P0019 0x0019
27 #define SMT_P001A 0x001a
28 #define SMT_P001B 0x001b
29 #define SMT_P001C 0x001c
30 #define SMT_P001D 0x001d
[all …]
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | spu.h | 23 #define MFC_PUT_CMD 0x20
24 #define MFC_PUTS_CMD 0x28
25 #define MFC_PUTR_CMD 0x30
26 #define MFC_PUTF_CMD 0x22
27 #define MFC_PUTB_CMD 0x21
28 #define MFC_PUTFS_CMD 0x2A
29 #define MFC_PUTBS_CMD 0x29
30 #define MFC_PUTRF_CMD 0x32
31 #define MFC_PUTRB_CMD 0x31
32 #define MFC_PUTL_CMD 0x24
[all …]
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| /openbmc/u-boot/board/BuR/brxre1/ |
| H A D | board.c | 33 #define ESC_KEY (0+19)
34 #define LCD_PWR (0+5)
35 #define PUSH_KEY (0+31)
40 #define RSTCTRL_ADDR 0x75
42 #define RSTCTRL_CTRLREG 0x01
44 #define RSTCTRL_SCRATCHREG 0x04
47 #define RSTCTRL_FORCE_PWR_NEN 0x0404
48 #define RSTCTRL_CAN_STB 0x4040
57 rc = i2c_get_chip_for_busnum(0, RSTCTRL_ADDR, 1, &i2cdev); in rstctrl_rw()
58 if (rc >= 0) { in rstctrl_rw()
[all …]
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| /openbmc/linux/arch/arm/boot/dts/nxp/mxs/ |
| H A D | imx28-pinfunc.h | 13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
|