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/openbmc/linux/include/dt-bindings/reset/
H A Dhisi,hi6220-resets.h9 #define PERIPH_RSTDIS0_MMC0 0x000
10 #define PERIPH_RSTDIS0_MMC1 0x001
11 #define PERIPH_RSTDIS0_MMC2 0x002
12 #define PERIPH_RSTDIS0_NANDC 0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005
15 #define PERIPH_RSTDIS0_USBOTG 0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007
17 #define PERIPH_RSTDIS1_HIFI 0x100
18 #define PERIPH_RSTDIS1_DIGACODEC 0x105
[all …]
/openbmc/linux/arch/m68k/coldfire/
H A Ddma_timer.c18 #define DMA_TIMER_0 (0x00)
19 #define DMA_TIMER_1 (0x40)
20 #define DMA_TIMER_2 (0x80)
21 #define DMA_TIMER_3 (0xc0)
23 #define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400)
24 #define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402)
25 #define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403)
26 #define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404)
27 #define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408)
28 #define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sc8280xp-mdss.yaml35 "^display-controller@[0-9a-f]+$":
41 "^displayport-controller@[0-9a-f]+$":
61 reg = <0x0ae00000 0x1000>;
79 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
80 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
83 iommus = <&apps_smmu 0x1000 0x402>;
91 reg = <0x0ae01000 0x8f000>,
92 <0x0aeb0000 0x2008>;
115 interrupts = <0>;
119 #size-cells = <0>;
[all …]
H A Dqcom,sm8350-mdss.yaml49 "^display-controller@[0-9a-f]+$":
55 "^displayport-controller@[0-9a-f]+$":
61 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
88 reg = <0x0ae00000 0x1000>;
91 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
92 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
104 iommus = <&apps_smmu 0x820 0x402>;
116 reg = <0x0ae01000 0x8f000>,
117 <0x0aeb0000 0x2008>;
[all …]
H A Dqcom,sm8250-mdss.yaml47 "^display-controller@[0-9a-f]+$":
53 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
83 reg = <0x0ae00000 0x1000>;
102 iommus = <&apps_smmu 0x820 0x402>;
110 reg = <0x0ae01000 0x8f000>,
111 <0x0aeb0000 0x2008>;
127 interrupts = <0>;
131 #size-cells = <0>;
133 port@0 {
[all …]
H A Dqcom,sm8450-mdss.yaml39 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
53 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
83 reg = <0x0ae00000 0x1000>;
86 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
87 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
104 iommus = <&apps_smmu 0x2800 0x402>;
112 reg = <0x0ae01000 0x8f000>,
113 <0x0aeb0000 0x2008>;
[all …]
H A Dqcom,sc7280-mdss.yaml45 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
65 "^edp@[0-9a-f]+$":
71 "^phy@[0-9a-f]+$":
97 reg = <0xae00000 0x1000>;
114 iommus = <&apps_smmu 0x900 0x402>;
119 reg = <0x0ae01000 0x8f000>,
120 <0x0aeb0000 0x2008>;
138 interrupts = <0>;
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/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dddr.c18 AR934X_SDRAM = 0,
32 [AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f },
33 [AR934X_DDR1] = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 },
34 [AR934X_DDR2] = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 },
51 cycle = 0xffff; in ar934x_ddr_init()
57 cycle = 0xff; in ar934x_ddr_init()
59 cycle = 0xffff; in ar934x_ddr_init()
62 ctl = 0; in ar934x_ddr_init()
63 cycle = 0xffff; /* DDR2 16bit */ in ar934x_ddr_init()
66 writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG); in ar934x_ddr_init()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_d.h27 #define mmIH_VMID_0_LUT 0xf50
28 #define mmIH_VMID_1_LUT 0xf51
29 #define mmIH_VMID_2_LUT 0xf52
30 #define mmIH_VMID_3_LUT 0xf53
31 #define mmIH_VMID_4_LUT 0xf54
32 #define mmIH_VMID_5_LUT 0xf55
33 #define mmIH_VMID_6_LUT 0xf56
34 #define mmIH_VMID_7_LUT 0xf57
35 #define mmIH_VMID_8_LUT 0xf58
36 #define mmIH_VMID_9_LUT 0xf59
[all …]
/openbmc/linux/drivers/staging/fbtft/
H A Dfb_bd663474.c31 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ in init_display()
35 write_reg(par, 0x100, 0x0000); /* power supply setup */ in init_display()
36 write_reg(par, 0x101, 0x0000); in init_display()
37 write_reg(par, 0x102, 0x3110); in init_display()
38 write_reg(par, 0x103, 0xe200); in init_display()
39 write_reg(par, 0x110, 0x009d); in init_display()
40 write_reg(par, 0x111, 0x0022); in init_display()
41 write_reg(par, 0x100, 0x0120); in init_display()
44 write_reg(par, 0x100, 0x3120); in init_display()
47 write_reg(par, 0x001, 0x0100); in init_display()
[all …]
/openbmc/linux/arch/sh/include/asm/
H A Dsh7760fb.h17 #define SH7760FB_PALETTE_MASK 0x00f8fcf8
20 #define SH7760FB_DMA_MASK 0x0C000000
26 #define LDICKR 0x400
27 #define LDMTR 0x402
29 #define LDDFR 0x404
31 #define LDDFR_COLOR_MASK 0x7F
32 #define LDSMR 0x406
34 #define LDSARU 0x408
35 #define LDSARL 0x40c
36 #define LDLAOR 0x410
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/openbmc/linux/tools/arch/x86/include/uapi/asm/
H A Dsvm.h5 #define SVM_EXIT_READ_CR0 0x000
6 #define SVM_EXIT_READ_CR2 0x002
7 #define SVM_EXIT_READ_CR3 0x003
8 #define SVM_EXIT_READ_CR4 0x004
9 #define SVM_EXIT_READ_CR8 0x008
10 #define SVM_EXIT_WRITE_CR0 0x010
11 #define SVM_EXIT_WRITE_CR2 0x012
12 #define SVM_EXIT_WRITE_CR3 0x013
13 #define SVM_EXIT_WRITE_CR4 0x014
14 #define SVM_EXIT_WRITE_CR8 0x018
[all …]
/openbmc/linux/arch/x86/include/uapi/asm/
H A Dsvm.h5 #define SVM_EXIT_READ_CR0 0x000
6 #define SVM_EXIT_READ_CR2 0x002
7 #define SVM_EXIT_READ_CR3 0x003
8 #define SVM_EXIT_READ_CR4 0x004
9 #define SVM_EXIT_READ_CR8 0x008
10 #define SVM_EXIT_WRITE_CR0 0x010
11 #define SVM_EXIT_WRITE_CR2 0x012
12 #define SVM_EXIT_WRITE_CR3 0x013
13 #define SVM_EXIT_WRITE_CR4 0x014
14 #define SVM_EXIT_WRITE_CR8 0x018
[all …]
/openbmc/linux/arch/x86/include/asm/uv/
H A Dbios.h32 #define UV_BIOS_EXTRA 0x10000
33 #define UV_BIOS_GET_PCI_TOPOLOGY 0x10001
34 #define UV_BIOS_GET_GEOINFO 0x10003
36 #define UV_BIOS_EXTRA_OP_MEM_COPYIN 0x1000
37 #define UV_BIOS_EXTRA_OP_MEM_COPYOUT 0x2000
38 #define UV_BIOS_EXTRA_OP_MASK 0x0fff
51 BIOS_STATUS_SUCCESS = 0,
69 #define UV_GAM_RANGE_TYPE_UNUSED 0 /* End of table */
97 #define UV_SYSTAB_VERSION_UV4 0x400 /* UV4 BIOS base version */
98 #define UV_SYSTAB_VERSION_UV4_1 0x401 /* + gpa_shift */
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dddr.c19 #define DDR_CTRL_UPD_MRS BIT(0)
22 #define DDR_REFRESH_M 0x3ff
23 #define DDR_REFRESH(x) ((x) & 0x3ff)
27 #define DDR_TRAS_S 0
28 #define DDR_TRAS_M 0x1f
30 #define DDR_TRCD_M 0xf
33 #define DDR_TRP_M 0xf
36 #define DDR_TRRD_M 0xf
39 #define DDR_TRFC_M 0x7f
42 #define DDR_TMRD_M 0xf
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dau8522_priv.h27 #define AU8522_ANALOG_MODE 0
88 #define AU8522_INPUT_CONTROL_REG081H 0x081
89 #define AU8522_PGA_CONTROL_REG082H 0x082
90 #define AU8522_CLAMPING_CONTROL_REG083H 0x083
92 #define AU8522_MODULE_CLOCK_CONTROL_REG0A3H 0x0A3
93 #define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H 0x0A4
94 #define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H 0x0A5
95 #define AU8522_AGC_CONTROL_RANGE_REG0A6H 0x0A6
96 #define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H 0x0A7
97 #define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A8
[all …]
/openbmc/linux/drivers/scsi/
H A Dmac_esp.c40 #define MAC_ESP_IO_BASE 0x50F00000
41 #define MAC_ESP_REGS_QUADRA (MAC_ESP_IO_BASE + 0x10000)
42 #define MAC_ESP_REGS_QUADRA2 (MAC_ESP_IO_BASE + 0xF000)
43 #define MAC_ESP_REGS_QUADRA3 (MAC_ESP_IO_BASE + 0x18000)
44 #define MAC_ESP_REGS_SPACING 0x402
45 #define MAC_ESP_PDMA_REG 0xF9800024
46 #define MAC_ESP_PDMA_REG_SPACING 0x4
47 #define MAC_ESP_PDMA_IO_OFFSET 0x100
99 return 0; in mac_esp_wait_for_empty_fifo()
121 return 0; in mac_esp_wait_for_dreq()
[all …]
H A Dzorro_esp.c60 unsigned char dma_addr; /* DMA address [0x0000] */
61 unsigned char dmapad2[0x7fff];
62 unsigned char dma_latch; /* DMA latch [0x8000] */
68 unsigned char dma_addr; /* DMA address [0x0000] */
69 unsigned char dmapad2[0xf];
70 unsigned char dma_latch; /* DMA latch [0x0010] */
76 unsigned char dma_led_ctrl; /* DMA led control [0x000] */
77 unsigned char dmapad1[0x0f];
78 unsigned char dma_addr0; /* DMA address (MSB) [0x010] */
79 unsigned char dmapad2[0x03];
[all …]
/openbmc/linux/drivers/net/ethernet/brocade/bna/
H A Dbna_hw_defs.h33 #define BFI_VLAN_WORD_MASK 0x1F
35 #define BFI_VLAN_BMASK_ALL 0xFF
38 #define BFI_MAX_COALESCING_TIMEO 0xFF /* in 5us units */
39 #define BFI_MAX_INTERPKT_COUNT 0xFF
40 #define BFI_MAX_INTERPKT_TIMEO 0xF /* in 0.5us units */
51 #define BFI_TX_MAX_WRR_QUOTA 0xFFF
54 #define BFI_TX_MAX_VECTORS_PER_PKT 0xFF
55 #define BFI_TX_MAX_DATA_PER_VECTOR 0xFFFF
56 #define BFI_TX_MAX_DATA_PER_PKT 0xFFFFFF
62 #define BFI_TX_PRIO_MAP_ALL 0xFF
[all …]
/openbmc/linux/drivers/mfd/
H A Drz-mtu3.c28 /******* MTU3 registers (original offset is +0x1200) *******/
30 [RZ_MTU3_CHAN_0] = MTU_8BIT_CH_0(0x104, 0x090, 0x100, 0x128, 0x101, 0x102, 0x103, 0x126),
31 [RZ_MTU3_CHAN_1] = MTU_8BIT_CH_1_2(0x184, 0x091, 0x185, 0x180, 0x194, 0x181, 0x182),
32 [RZ_MTU3_CHAN_2] = MTU_8BIT_CH_1_2(0x204, 0x092, 0x205, 0x200, 0x20c, 0x201, 0x202),
33 …[RZ_MTU3_CHAN_3] = MTU_8BIT_CH_3_4_6_7(0x008, 0x093, 0x02c, 0x000, 0x04c, 0x002, 0x004, 0x005, 0x0…
34 …[RZ_MTU3_CHAN_4] = MTU_8BIT_CH_3_4_6_7(0x009, 0x094, 0x02d, 0x001, 0x04d, 0x003, 0x006, 0x007, 0x0…
35 …[RZ_MTU3_CHAN_5] = MTU_8BIT_CH_5(0xab2, 0x1eb, 0xab4, 0xab6, 0xa84, 0xa85, 0xa86, 0xa94, 0xa95, 0x…
36 …[RZ_MTU3_CHAN_6] = MTU_8BIT_CH_3_4_6_7(0x808, 0x893, 0x82c, 0x800, 0x84c, 0x802, 0x804, 0x805, 0x8…
37 …[RZ_MTU3_CHAN_7] = MTU_8BIT_CH_3_4_6_7(0x809, 0x894, 0x82d, 0x801, 0x84d, 0x803, 0x806, 0x807, 0x8…
38 [RZ_MTU3_CHAN_8] = MTU_8BIT_CH_8(0x404, 0x098, 0x400, 0x406, 0x401, 0x402, 0x403)
[all …]
/openbmc/linux/fs/ntfs3/
H A Dlznt.c20 #define LZNT_CHUNK_SIZE 0x1000
41 size_t len = 0; in get_match_len()
51 size_t len1 = 0, len2 = 0; in longest_match_std()
55 ((40543U * ((((src[0] << 4) ^ src[1]) << 4) ^ src[2])) >> 4) & in longest_match_std()
60 if (hash[0] >= ctx->unc && hash[0] < src && hash[0][0] == src[0] && in longest_match_std()
61 hash[0][1] == src[1] && hash[0][2] == src[2]) { in longest_match_std()
65 hash[0] + 3, ctx->max_len - 3); in longest_match_std()
68 if (hash[1] >= ctx->unc && hash[1] < src && hash[1][0] == src[0] && in longest_match_std()
81 ctx->best_match = hash[0]; in longest_match_std()
84 hash[1] = hash[0]; in longest_match_std()
[all …]
/openbmc/linux/include/linux/mfd/mt6331/
H A Dregisters.h10 #define MT6331_STRUP_CON0 0x0
11 #define MT6331_STRUP_CON2 0x2
12 #define MT6331_STRUP_CON3 0x4
13 #define MT6331_STRUP_CON4 0x6
14 #define MT6331_STRUP_CON5 0x8
15 #define MT6331_STRUP_CON6 0xA
16 #define MT6331_STRUP_CON7 0xC
17 #define MT6331_STRUP_CON8 0xE
18 #define MT6331_STRUP_CON9 0x10
19 #define MT6331_STRUP_CON10 0x12
[all …]
/openbmc/linux/include/uapi/linux/
H A Delf.h26 #define PT_NULL 0
34 #define PT_LOOS 0x60000000 /* OS-specific */
35 #define PT_HIOS 0x6fffffff /* OS-specific */
36 #define PT_LOPROC 0x70000000
37 #define PT_HIPROC 0x7fffffff
38 #define PT_GNU_EH_FRAME (PT_LOOS + 0x474e550)
39 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
40 #define PT_GNU_RELRO (PT_LOOS + 0x474e552)
41 #define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
45 #define PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 0x2)
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dddr.c19 #define DDR_CTRL_UPD_MRS BIT(0)
22 #define DDR_REFRESH_M 0x3ff
26 #define DDR_TRAS_S 0
27 #define DDR_TRAS_M 0x1f
29 #define DDR_TRCD_M 0xf
32 #define DDR_TRP_M 0xf
35 #define DDR_TRRD_M 0xf
38 #define DDR_TRFC_M 0x7f
41 #define DDR_TMRD_M 0xf
44 #define DDR_CAS_L_M 0x17
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Ddc.h12 /* CMD register 0x000 ~ 0x43 */
14 /* Address 0x000 ~ 0x002 */
21 /* Address 0x008 ~ 0x00a */
28 /* Address 0x010 ~ 0x012 */
35 /* Address 0x018 ~ 0x01a */
42 /* Address 0x028 */
47 /* Address 0x030 ~ 0x033 */
55 /* Address 0x036 ~ 0x03e */
68 /* Address 0x040 ~ 0x043 */
80 /* COM register 0x300 ~ 0x329 */
[all …]

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