/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/ |
H A D | dma_ch_0_regs.h | 22 #define mmDMA_CH_0_CFG0 0x401000 24 #define mmDMA_CH_0_CFG1 0x401004 26 #define mmDMA_CH_0_ERRMSG_ADDR_LO 0x401008 28 #define mmDMA_CH_0_ERRMSG_ADDR_HI 0x40100C 30 #define mmDMA_CH_0_ERRMSG_WDATA 0x401010 32 #define mmDMA_CH_0_RD_COMP_ADDR_LO 0x401014 34 #define mmDMA_CH_0_RD_COMP_ADDR_HI 0x401018 36 #define mmDMA_CH_0_RD_COMP_WDATA 0x40101C 38 #define mmDMA_CH_0_WR_COMP_ADDR_LO 0x401020 40 #define mmDMA_CH_0_WR_COMP_ADDR_HI 0x401024 [all …]
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H A D | goya_blocks.h | 16 #define mmPCI_NRTR_BASE 0x7FFC000000ull 17 #define PCI_NRTR_MAX_OFFSET 0x608 18 #define PCI_NRTR_SECTION 0x4000 19 #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull 20 #define PCI_RD_REGULATOR_MAX_OFFSET 0x74 21 #define PCI_RD_REGULATOR_SECTION 0x1000 22 #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull 23 #define PCI_WR_REGULATOR_MAX_OFFSET 0x74 24 #define PCI_WR_REGULATOR_SECTION 0x3B000 25 #define mmMME1_RTR_BASE 0x7FFC040000ull [all …]
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/cfg/ |
H A D | sc.c | 19 #define IWL_SC_NVM_VERSION 0x0a1d 22 #define IWL_SC_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_SC_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_SC_DCCM2_OFFSET 0x880000 25 #define IWL_SC_DCCM2_LEN 0x8000 26 #define IWL_SC_SMEM_OFFSET 0x400000 27 #define IWL_SC_SMEM_LEN 0xD0000 79 .mac_addr_from_csr = 0x30, \ 85 .min_umac_error_event_table = 0xD0000, \ 86 .d3_debug_data_base_addr = 0x401000, \ [all …]
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H A D | bz.c | 19 #define IWL_BZ_NVM_VERSION 0x0a1d 22 #define IWL_BZ_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_BZ_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_BZ_DCCM2_OFFSET 0x880000 25 #define IWL_BZ_DCCM2_LEN 0x8000 26 #define IWL_BZ_SMEM_OFFSET 0x400000 27 #define IWL_BZ_SMEM_LEN 0xD0000 82 .mac_addr_from_csr = 0x30, \ 88 .min_umac_error_event_table = 0xD0000, \ 89 .d3_debug_data_base_addr = 0x401000, \ [all …]
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H A D | 9000.c | 19 #define IWL9000_NVM_VERSION 0x0a1d 22 #define IWL9000_DCCM_OFFSET 0x800000 23 #define IWL9000_DCCM_LEN 0x18000 24 #define IWL9000_DCCM2_OFFSET 0x880000 25 #define IWL9000_DCCM2_LEN 0x8000 26 #define IWL9000_SMEM_OFFSET 0x400000 27 #define IWL9000_SMEM_LEN 0x68000 92 .mac_addr_from_csr = 0x380, \ 95 .min_umac_error_event_table = 0x800000, \ 96 .d3_debug_data_base_addr = 0x401000, \ [all …]
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H A D | ax210.c | 19 #define IWL_AX210_NVM_VERSION 0x0a1d 22 #define IWL_AX210_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_AX210_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_AX210_DCCM2_OFFSET 0x880000 25 #define IWL_AX210_DCCM2_LEN 0x8000 26 #define IWL_AX210_SMEM_OFFSET 0x400000 27 #define IWL_AX210_SMEM_LEN 0xD0000 96 .mac_addr_from_csr = 0x380, \ 103 .min_umac_error_event_table = 0x400000, \ 104 .d3_debug_data_base_addr = 0x401000, \ [all …]
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H A D | 22000.c | 19 #define IWL_22000_NVM_VERSION 0x0a1d 22 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_22000_DCCM2_OFFSET 0x880000 25 #define IWL_22000_DCCM2_LEN 0x8000 26 #define IWL_22000_SMEM_OFFSET 0x400000 27 #define IWL_22000_SMEM_LEN 0xD0000 84 .mac_addr_from_csr = 0x380, \ 91 .min_umac_error_event_table = 0x400000, \ 92 .d3_debug_data_base_addr = 0x401000, \ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | microchip,sparx5-switch.yaml | 34 pattern: "^switch@[0-9a-f]+$" 83 const: 0 86 "^port@[0-9a-f]+$": 111 minimum: 0 142 reg = <0 0x401000>, 143 <0x10004000 0x7fc000>, 144 <0x11010000 0xaf0000>; 148 resets = <&reset 0>; 152 #size-cells = <0>; 154 port0: port@0 { [all …]
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/openbmc/linux/arch/arm64/boot/dts/microchip/ |
H A D | sparx5.dtsi | 28 #size-cells = <0>; 39 cpu0: cpu@0 { 42 reg = <0x0>; 49 reg = <0x1>; 81 #clock-cells = <0>; 89 reg = <0x6 0x1110000c 0x24>; 94 #clock-cells = <0>; 100 #clock-cells = <0>; 116 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ 117 <0x6 0x00340000 0xc0000>, /* GICR */ [all …]
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/openbmc/linux/tools/testing/selftests/kvm/aarch64/ |
H A D | vgic_init.c | 23 #define GICR_TYPER 0x8 57 TEST_ASSERT(val == want, "%s; want '0x%x', got '0x%x'", msg, want, val); in v3_redist_reg_get() 63 GUEST_SYNC(0); in guest_code() 72 return __vcpu_run(vcpu) ? -errno : 0; in run_vcpu() 114 .size = 0x10000, 115 .alignment = 0x10000, 120 .size = NR_VCPUS * 0x20000, 121 .alignment = 0x10000, 126 .size = 0x1000, 127 .alignment = 0x1000, [all …]
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
H A D | ctxnv40.c | 31 * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state" 35 * opcode 0x60000d is called before resuming normal operation. 37 * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001)) 38 * and calls 0x60000d before resuming normal operation. 40 * and if true 0x800001 is called with count=0, pos=0, the flag is cleared 44 * flag 10. If it's set, they only transfer the small 0x300 byte block 50 * - There's a number of places where context offset 0 (where we place 51 * the PRAMIN offset of the context) is loaded into either 0x408000, 52 * 0x408004 or 0x408008. Not sure what's up there either. 53 * - The ctxprogs for some cards save 0x400a00 again during the cleanup [all …]
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/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/ |
H A D | gaudi_blocks.h | 16 #define mmNIC0_PHY0_BASE 0x0ull 17 #define NIC0_PHY0_MAX_OFFSET 0x9F13 18 #define mmMME0_ACC_BASE 0x7FFC020000ull 19 #define MME0_ACC_MAX_OFFSET 0x5C00 20 #define MME0_ACC_SECTION 0x20000 21 #define mmMME0_SBAB_BASE 0x7FFC040000ull 22 #define MME0_SBAB_MAX_OFFSET 0x5800 23 #define MME0_SBAB_SECTION 0x1000 24 #define mmMME0_PRTN_BASE 0x7FFC041000ull 25 #define MME0_PRTN_MAX_OFFSET 0x5000 [all …]
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/openbmc/qemu/target/xtensa/core-lx106/ |
H A D | xtensa-modules.c.inc | 31 { "MMID", 89, 0 }, 32 { "DDR", 104, 0 }, 33 { "176", 176, 0 }, 34 { "208", 208, 0 }, 35 { "INTERRUPT", 226, 0 }, 36 { "INTCLEAR", 227, 0 }, 37 { "CCOUNT", 234, 0 }, 38 { "PRID", 235, 0 }, 39 { "ICOUNT", 236, 0 }, 40 { "CCOMPARE0", 240, 0 }, [all …]
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/openbmc/qemu/target/xtensa/core-sample_controller/ |
H A D | xtensa-modules.c.inc | 32 { "MMID", 89, 0 }, 33 { "DDR", 104, 0 }, 34 { "CONFIGID0", 176, 0 }, 35 { "CONFIGID1", 208, 0 }, 36 { "INTERRUPT", 226, 0 }, 37 { "INTCLEAR", 227, 0 }, 38 { "CCOUNT", 234, 0 }, 39 { "PRID", 235, 0 }, 40 { "ICOUNT", 236, 0 }, 41 { "CCOMPARE0", 240, 0 }, [all …]
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/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
H A D | gaudi2_blocks_linux_driver.h | 16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull 17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000 19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull 20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000 21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000 22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull 23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000 24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000 25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull [all …]
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/openbmc/qemu/target/xtensa/core-dc233c/ |
H A D | xtensa-modules.c.inc | 3 Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc. 32 { "LBEG", 0, 0 }, 33 { "LEND", 1, 0 }, 34 { "LCOUNT", 2, 0 }, 35 { "ACCLO", 16, 0 }, 36 { "ACCHI", 17, 0 }, 37 { "M0", 32, 0 }, 38 { "M1", 33, 0 }, 39 { "M2", 34, 0 }, 40 { "M3", 35, 0 }, [all …]
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/openbmc/qemu/target/xtensa/core-de212/ |
H A D | xtensa-modules.c.inc | 32 { "LBEG", 0, 0 }, 33 { "LEND", 1, 0 }, 34 { "LCOUNT", 2, 0 }, 35 { "ACCLO", 16, 0 }, 36 { "ACCHI", 17, 0 }, 37 { "M0", 32, 0 }, 38 { "M1", 33, 0 }, 39 { "M2", 34, 0 }, 40 { "M3", 35, 0 }, 41 { "MMID", 89, 0 }, [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
H A D | nbio_7_2_0_offset.h | 26 // base address: 0x0 27 …BIF_CFG_DEV0_RC_VENDOR_ID 0x0000 28 …BIF_CFG_DEV0_RC_DEVICE_ID 0x0002 29 …BIF_CFG_DEV0_RC_COMMAND 0x0004 30 …BIF_CFG_DEV0_RC_STATUS 0x0006 31 …BIF_CFG_DEV0_RC_REVISION_ID 0x0008 32 …BIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009 33 …BIF_CFG_DEV0_RC_SUB_CLASS 0x000a 34 …BIF_CFG_DEV0_RC_BASE_CLASS 0x000b 35 …BIF_CFG_DEV0_RC_CACHE_LINE 0x000c [all …]
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H A D | nbio_7_7_0_offset.h | 29 // base address: 0x0 30 …NBCFG_SCRATCH_4 0x0078 34 // base address: 0x0 35 …BIF_CFG_DEV0_RC_VENDOR_ID 0x0000 36 …BIF_CFG_DEV0_RC_DEVICE_ID 0x0002 37 …BIF_CFG_DEV0_RC_COMMAND 0x0004 38 …BIF_CFG_DEV0_RC_STATUS 0x0006 39 …BIF_CFG_DEV0_RC_REVISION_ID 0x0008 40 …BIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009 41 …BIF_CFG_DEV0_RC_SUB_CLASS 0x000a [all …]
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/openbmc/qemu/target/xtensa/core-dc232b/ |
H A D | xtensa-modules.c.inc | 29 { "LBEG", 0, 0 }, 30 { "LEND", 1, 0 }, 31 { "LCOUNT", 2, 0 }, 32 { "ACCLO", 16, 0 }, 33 { "ACCHI", 17, 0 }, 34 { "M0", 32, 0 }, 35 { "M1", 33, 0 }, 36 { "M2", 34, 0 }, 37 { "M3", 35, 0 }, 38 { "PTEVADDR", 83, 0 }, [all …]
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/openbmc/qemu/target/xtensa/core-de233_fpu/ |
H A D | xtensa-modules.c.inc | 31 { "LBEG", 0, 0 }, 32 { "LEND", 1, 0 }, 33 { "LCOUNT", 2, 0 }, 34 { "BR", 4, 0 }, 35 { "ACCLO", 16, 0 }, 36 { "ACCHI", 17, 0 }, 37 { "M0", 32, 0 }, 38 { "M1", 33, 0 }, 39 { "M2", 34, 0 }, 40 { "M3", 35, 0 }, [all …]
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/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/ |
H A D | xtensa-modules.c.inc | 31 { "LBEG", 0, 0 }, 32 { "LEND", 1, 0 }, 33 { "LCOUNT", 2, 0 }, 34 { "BR", 4, 0 }, 35 { "PTEVADDR", 83, 0 }, 36 { "DDR", 104, 0 }, 37 { "CONFIGID0", 176, 0 }, 38 { "CONFIGID1", 208, 0 }, 39 { "INTERRUPT", 226, 0 }, 40 { "INTCLEAR", 227, 0 }, [all …]
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/openbmc/qemu/target/xtensa/core-dsp3400/ |
H A D | xtensa-modules.c.inc | 31 { "LBEG", 0, 0 }, 32 { "LEND", 1, 0 }, 33 { "LCOUNT", 2, 0 }, 34 { "BR", 4, 0 }, 35 { "MMID", 89, 0 }, 36 { "DDR", 104, 0 }, 37 { "176", 176, 0 }, 38 { "208", 208, 0 }, 39 { "INTERRUPT", 226, 0 }, 40 { "INTCLEAR", 227, 0 }, [all …]
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