119898ce9SJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 219898ce9SJohannes Berg /* 319898ce9SJohannes Berg * Copyright (C) 2015-2017 Intel Deutschland GmbH 419898ce9SJohannes Berg * Copyright (C) 2018-2023 Intel Corporation 519898ce9SJohannes Berg */ 619898ce9SJohannes Berg #include <linux/module.h> 719898ce9SJohannes Berg #include <linux/stringify.h> 819898ce9SJohannes Berg #include "iwl-config.h" 919898ce9SJohannes Berg #include "iwl-prph.h" 1019898ce9SJohannes Berg #include "fw/api/txq.h" 1119898ce9SJohannes Berg 1219898ce9SJohannes Berg /* Highest firmware API version supported */ 13399762deSGregory Greenman #define IWL_BZ_UCODE_API_MAX 83 1419898ce9SJohannes Berg 1519898ce9SJohannes Berg /* Lowest firmware API version supported */ 16a13707f7SJohannes Berg #define IWL_BZ_UCODE_API_MIN 80 1719898ce9SJohannes Berg 1819898ce9SJohannes Berg /* NVM versions */ 1919898ce9SJohannes Berg #define IWL_BZ_NVM_VERSION 0x0a1d 2019898ce9SJohannes Berg 2119898ce9SJohannes Berg /* Memory offsets and lengths */ 2219898ce9SJohannes Berg #define IWL_BZ_DCCM_OFFSET 0x800000 /* LMAC1 */ 2319898ce9SJohannes Berg #define IWL_BZ_DCCM_LEN 0x10000 /* LMAC1 */ 2419898ce9SJohannes Berg #define IWL_BZ_DCCM2_OFFSET 0x880000 2519898ce9SJohannes Berg #define IWL_BZ_DCCM2_LEN 0x8000 2619898ce9SJohannes Berg #define IWL_BZ_SMEM_OFFSET 0x400000 2719898ce9SJohannes Berg #define IWL_BZ_SMEM_LEN 0xD0000 2819898ce9SJohannes Berg 2931aeae24SJohannes Berg #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0" 3031aeae24SJohannes Berg #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0" 3131aeae24SJohannes Berg #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0" 3231aeae24SJohannes Berg #define IWL_BZ_A_FM_B_FW_PRE "iwlwifi-bz-a0-fm-b0" 3331aeae24SJohannes Berg #define IWL_BZ_A_FM_C_FW_PRE "iwlwifi-bz-a0-fm-c0" 3431aeae24SJohannes Berg #define IWL_BZ_A_FM4_B_FW_PRE "iwlwifi-bz-a0-fm4-b0" 3531aeae24SJohannes Berg #define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0" 3631aeae24SJohannes Berg #define IWL_GL_C_FM_C_FW_PRE "iwlwifi-gl-c0-fm-c0" 3719898ce9SJohannes Berg 3819898ce9SJohannes Berg #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 3931aeae24SJohannes Berg IWL_BZ_A_HR_B_FW_PRE "-" __stringify(api) ".ucode" 4019898ce9SJohannes Berg #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \ 4131aeae24SJohannes Berg IWL_BZ_A_GF_A_FW_PRE "-" __stringify(api) ".ucode" 4219898ce9SJohannes Berg #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \ 4331aeae24SJohannes Berg IWL_BZ_A_GF4_A_FW_PRE "-" __stringify(api) ".ucode" 4419898ce9SJohannes Berg #define IWL_BZ_A_FM_B_MODULE_FIRMWARE(api) \ 4531aeae24SJohannes Berg IWL_BZ_A_FM_B_FW_PRE "-" __stringify(api) ".ucode" 4619898ce9SJohannes Berg #define IWL_BZ_A_FM_C_MODULE_FIRMWARE(api) \ 4731aeae24SJohannes Berg IWL_BZ_A_FM_C_FW_PRE "-" __stringify(api) ".ucode" 4819898ce9SJohannes Berg #define IWL_BZ_A_FM4_B_MODULE_FIRMWARE(api) \ 4931aeae24SJohannes Berg IWL_BZ_A_FM4_B_FW_PRE "-" __stringify(api) ".ucode" 5019898ce9SJohannes Berg #define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \ 5131aeae24SJohannes Berg IWL_GL_B_FM_B_FW_PRE "-" __stringify(api) ".ucode" 5219898ce9SJohannes Berg #define IWL_GL_C_FM_C_MODULE_FIRMWARE(api) \ 5331aeae24SJohannes Berg IWL_GL_C_FM_C_FW_PRE "-" __stringify(api) ".ucode" 5419898ce9SJohannes Berg 5519898ce9SJohannes Berg static const struct iwl_base_params iwl_bz_base_params = { 5619898ce9SJohannes Berg .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 5719898ce9SJohannes Berg .num_of_queues = 512, 5819898ce9SJohannes Berg .max_tfd_queue_size = 65536, 5919898ce9SJohannes Berg .shadow_ram_support = true, 6019898ce9SJohannes Berg .led_compensation = 57, 6119898ce9SJohannes Berg .wd_timeout = IWL_LONG_WD_TIMEOUT, 6219898ce9SJohannes Berg .max_event_log_size = 512, 6319898ce9SJohannes Berg .shadow_reg_enable = true, 6419898ce9SJohannes Berg .pcie_l1_allowed = true, 6519898ce9SJohannes Berg }; 6619898ce9SJohannes Berg 6719898ce9SJohannes Berg #define IWL_DEVICE_BZ_COMMON \ 6819898ce9SJohannes Berg .ucode_api_max = IWL_BZ_UCODE_API_MAX, \ 6919898ce9SJohannes Berg .ucode_api_min = IWL_BZ_UCODE_API_MIN, \ 7019898ce9SJohannes Berg .led_mode = IWL_LED_RF_STATE, \ 7119898ce9SJohannes Berg .nvm_hw_section_num = 10, \ 7219898ce9SJohannes Berg .non_shared_ant = ANT_B, \ 7319898ce9SJohannes Berg .dccm_offset = IWL_BZ_DCCM_OFFSET, \ 7419898ce9SJohannes Berg .dccm_len = IWL_BZ_DCCM_LEN, \ 7519898ce9SJohannes Berg .dccm2_offset = IWL_BZ_DCCM2_OFFSET, \ 7619898ce9SJohannes Berg .dccm2_len = IWL_BZ_DCCM2_LEN, \ 7719898ce9SJohannes Berg .smem_offset = IWL_BZ_SMEM_OFFSET, \ 7819898ce9SJohannes Berg .smem_len = IWL_BZ_SMEM_LEN, \ 7919898ce9SJohannes Berg .apmg_not_supported = true, \ 8019898ce9SJohannes Berg .trans.mq_rx_supported = true, \ 8119898ce9SJohannes Berg .vht_mu_mimo_supported = true, \ 8219898ce9SJohannes Berg .mac_addr_from_csr = 0x30, \ 8319898ce9SJohannes Berg .nvm_ver = IWL_BZ_NVM_VERSION, \ 8419898ce9SJohannes Berg .trans.rf_id = true, \ 8519898ce9SJohannes Berg .trans.gen2 = true, \ 8619898ce9SJohannes Berg .nvm_type = IWL_NVM_EXT, \ 8719898ce9SJohannes Berg .dbgc_supported = true, \ 8819898ce9SJohannes Berg .min_umac_error_event_table = 0xD0000, \ 8919898ce9SJohannes Berg .d3_debug_data_base_addr = 0x401000, \ 9019898ce9SJohannes Berg .d3_debug_data_length = 60 * 1024, \ 9119898ce9SJohannes Berg .mon_smem_regs = { \ 9219898ce9SJohannes Berg .write_ptr = { \ 9319898ce9SJohannes Berg .addr = LDBG_M2S_BUF_WPTR, \ 9419898ce9SJohannes Berg .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 9519898ce9SJohannes Berg }, \ 9619898ce9SJohannes Berg .cycle_cnt = { \ 9719898ce9SJohannes Berg .addr = LDBG_M2S_BUF_WRAP_CNT, \ 9819898ce9SJohannes Berg .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 9919898ce9SJohannes Berg }, \ 10019898ce9SJohannes Berg }, \ 10119898ce9SJohannes Berg .trans.umac_prph_offset = 0x300000, \ 10219898ce9SJohannes Berg .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 10319898ce9SJohannes Berg .trans.base_params = &iwl_bz_base_params, \ 10419898ce9SJohannes Berg .min_txq_size = 128, \ 10519898ce9SJohannes Berg .gp2_reg_addr = 0xd02c68, \ 10619898ce9SJohannes Berg .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 10719898ce9SJohannes Berg .mon_dram_regs = { \ 10819898ce9SJohannes Berg .write_ptr = { \ 10919898ce9SJohannes Berg .addr = DBGC_CUR_DBGBUF_STATUS, \ 11019898ce9SJohannes Berg .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 11119898ce9SJohannes Berg }, \ 11219898ce9SJohannes Berg .cycle_cnt = { \ 11319898ce9SJohannes Berg .addr = DBGC_DBGBUF_WRAP_AROUND, \ 11419898ce9SJohannes Berg .mask = 0xffffffff, \ 11519898ce9SJohannes Berg }, \ 11619898ce9SJohannes Berg .cur_frag = { \ 11719898ce9SJohannes Berg .addr = DBGC_CUR_DBGBUF_STATUS, \ 11819898ce9SJohannes Berg .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 11919898ce9SJohannes Berg }, \ 12019898ce9SJohannes Berg }, \ 12119898ce9SJohannes Berg .mon_dbgi_regs = { \ 12219898ce9SJohannes Berg .write_ptr = { \ 12319898ce9SJohannes Berg .addr = DBGI_SRAM_FIFO_POINTERS, \ 12419898ce9SJohannes Berg .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 12519898ce9SJohannes Berg }, \ 12619898ce9SJohannes Berg } 12719898ce9SJohannes Berg 12819898ce9SJohannes Berg #define IWL_DEVICE_BZ \ 12919898ce9SJohannes Berg IWL_DEVICE_BZ_COMMON, \ 13019898ce9SJohannes Berg .ht_params = &iwl_22000_ht_params 13119898ce9SJohannes Berg 13219898ce9SJohannes Berg #define IWL_DEVICE_GL_A \ 13319898ce9SJohannes Berg IWL_DEVICE_BZ_COMMON, \ 13419898ce9SJohannes Berg .ht_params = &iwl_gl_a_ht_params 13519898ce9SJohannes Berg 13619898ce9SJohannes Berg /* 1376e1cae8bSJohannes Berg * This size was picked according to 8 MSDUs inside 512 A-MSDUs in an 13819898ce9SJohannes Berg * A-MPDU, with additional overhead to account for processing time. 13919898ce9SJohannes Berg */ 1406e1cae8bSJohannes Berg #define IWL_NUM_RBDS_BZ_EHT (512 * 16) 14119898ce9SJohannes Berg 14219898ce9SJohannes Berg const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 14319898ce9SJohannes Berg .device_family = IWL_DEVICE_FAMILY_BZ, 14419898ce9SJohannes Berg .base_params = &iwl_bz_base_params, 14519898ce9SJohannes Berg .mq_rx_supported = true, 14619898ce9SJohannes Berg .rf_id = true, 14719898ce9SJohannes Berg .gen2 = true, 14819898ce9SJohannes Berg .integrated = true, 14919898ce9SJohannes Berg .umac_prph_offset = 0x300000, 15019898ce9SJohannes Berg .xtal_latency = 12000, 15119898ce9SJohannes Berg .low_latency_xtal = true, 15219898ce9SJohannes Berg .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 15319898ce9SJohannes Berg }; 15419898ce9SJohannes Berg 155*2c4a7b50SJohannes Berg const struct iwl_cfg_trans_params iwl_gl_trans_cfg = { 156*2c4a7b50SJohannes Berg .device_family = IWL_DEVICE_FAMILY_BZ, 157*2c4a7b50SJohannes Berg .base_params = &iwl_bz_base_params, 158*2c4a7b50SJohannes Berg .mq_rx_supported = true, 159*2c4a7b50SJohannes Berg .rf_id = true, 160*2c4a7b50SJohannes Berg .gen2 = true, 161*2c4a7b50SJohannes Berg .umac_prph_offset = 0x300000, 162*2c4a7b50SJohannes Berg .xtal_latency = 12000, 163*2c4a7b50SJohannes Berg .low_latency_xtal = true, 164*2c4a7b50SJohannes Berg }; 165*2c4a7b50SJohannes Berg 16619898ce9SJohannes Berg const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 16719898ce9SJohannes Berg 1683fd31289SJohannes Berg const struct iwl_cfg iwl_cfg_bz = { 1693fd31289SJohannes Berg .fw_name_mac = "bz", 17019898ce9SJohannes Berg .uhb_supported = true, 17119898ce9SJohannes Berg IWL_DEVICE_BZ, 1726769207fSJohannes Berg .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1736e1cae8bSJohannes Berg .num_rbds = IWL_NUM_RBDS_BZ_EHT, 17419898ce9SJohannes Berg }; 17519898ce9SJohannes Berg 1763fd31289SJohannes Berg const struct iwl_cfg iwl_cfg_gl = { 1773fd31289SJohannes Berg .fw_name_mac = "gl", 17819898ce9SJohannes Berg .uhb_supported = true, 17919898ce9SJohannes Berg IWL_DEVICE_BZ, 1806769207fSJohannes Berg .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 1816e1cae8bSJohannes Berg .num_rbds = IWL_NUM_RBDS_BZ_EHT, 18219898ce9SJohannes Berg }; 18319898ce9SJohannes Berg 18419898ce9SJohannes Berg 18519898ce9SJohannes Berg MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 18619898ce9SJohannes Berg MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 18719898ce9SJohannes Berg MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 18819898ce9SJohannes Berg MODULE_FIRMWARE(IWL_BZ_A_FM_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 18919898ce9SJohannes Berg MODULE_FIRMWARE(IWL_BZ_A_FM_C_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 19019898ce9SJohannes Berg MODULE_FIRMWARE(IWL_BZ_A_FM4_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 19119898ce9SJohannes Berg MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 19219898ce9SJohannes Berg MODULE_FIRMWARE(IWL_GL_C_FM_C_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 19395eec168STakashi Iwai 19495eec168STakashi Iwai MODULE_FIRMWARE("iwlwifi-gl-c0-fm-c0.pnvm"); 195