Searched +full:0 +full:x40020800 (Results 1 – 4 of 4) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/dma/ |
H A D | st,stm32-dmamux.yaml | 45 reg = <0x40020800 0x3c>;
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/openbmc/qemu/hw/arm/ |
H A D | stm32f405_soc.c | 33 #define RCC_ADDR 0x40023800 34 #define SYSCFG_ADD 0x40013800 35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800, 36 0x40004C00, 0x40005000, 0x40011400, 37 0x40007800, 0x40007C00 }; 39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400, 40 0x40000800, 0x40000C00 }; 41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200, 42 0x40012300, 0x40012400, 0x40012500 }; 43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00, [all …]
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H A D | stm32l4x5_soc.c | 36 #define FLASH_BASE_ADDRESS 0x08000000 37 #define SRAM1_BASE_ADDRESS 0x20000000 39 #define SRAM2_BASE_ADDRESS 0x10000000 42 #define EXTI_ADDR 0x40010400 43 #define SYSCFG_ADDR 0x40010000 53 6, /* GPIO[0] */ 81 #define RCC_BASE_ADDRESS 0x40021000 114 { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 }, 115 { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 }, 116 { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 }, [all …]
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/openbmc/linux/arch/arm/boot/dts/st/ |
H A D | stm32h743.dtsi | 54 #clock-cells = <0>; 56 clock-frequency = <0>; 60 #clock-cells = <0>; 66 #clock-cells = <0>; 68 clock-frequency = <0>; 75 reg = <0x40000c00 0x400>; 82 #size-cells = <0>; 84 reg = <0x40002400 0x400>; 95 trigger@0 { 97 reg = <0>; [all …]
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