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/openbmc/u-boot/arch/arm/dts/
H A Dk3-am65.dtsi59 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
60 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
61 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
62 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
63 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
65 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
66 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
67 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
68 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
69 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
[all …]
H A Dimx7s.dtsi94 #size-cells = <0>;
96 cpu0: cpu@0 {
99 reg = <0>;
108 #clock-cells = <0>;
115 #clock-cells = <0>;
124 #phy-cells = <0>;
131 #phy-cells = <0>;
150 #size-cells = <0>;
152 port@0 {
153 reg = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/ti/
H A Dk3-udma.yaml56 for source thread IDs (rx): 0 - 0x7fff
57 for destination thread IDs (tx): 0x8000 - 0xffff
153 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
159 reg = <0x0 0x31150000 0x0 0x100>,
160 <0x0 0x34000000 0x0 0x100000>,
161 <0x0 0x35000000 0x0 0x100000>;
172 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
173 <0x2>; /* TX_CHAN */
174 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
175 <0x5>; /* RX_CHAN */
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
[all …]
H A Dimx8mq.dtsi47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
[all …]
H A Dimx8mn.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
[all …]
H A Dimx8mp.dtsi48 #size-cells = <0>;
50 A53_0: cpu@0 {
53 reg = <0x0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
73 reg = <0x1>;
77 i-cache-size = <0x8000>;
80 d-cache-size = <0x8000>;
91 reg = <0x2>;
95 i-cache-size = <0x8000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7s.dtsi56 #size-cells = <0>;
63 arm,psci-suspend-param = <0x0010000>;
71 cpu0: cpu@0 {
74 reg = <0>;
94 opp-supported-hw = <0xf>, <0xf>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
116 #phy-cells = <0>;
124 #phy-cells = <0>;
143 #size-cells = <0>;
[all …]
/openbmc/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dimx-regs.h11 #define ROM_SW_INFO_ADDR 0x000001E8
12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x00017FFF
15 #define CAAM_ARB_BASE_ADDR 0x00100000
16 #define CAAM_ARB_END_ADDR 0x00107FFF
17 #define GIC400_ARB_BASE_ADDR 0x31000000
18 #define GIC400_ARB_END_ADDR 0x31007FFF
19 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
20 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
21 #define M4_BOOTROM_BASE_ADDR 0x00180000
[all …]
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc12 OPC_MOVGR2SCR = 0x00000800,
13 OPC_MOVSCR2GR = 0x00000c00,
14 OPC_CLZ_W = 0x00001400,
15 OPC_CTZ_W = 0x00001c00,
16 OPC_CLZ_D = 0x00002400,
17 OPC_CTZ_D = 0x00002c00,
18 OPC_REVB_2H = 0x00003000,
19 OPC_REVB_2W = 0x00003800,
20 OPC_REVB_D = 0x00003c00,
21 OPC_SEXT_H = 0x00005800,
[all …]