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/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-wb45n.dtsi21 reg = <0x20000000 0x4000000>;
49 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb &pinctrl_nand_oe_we>;
54 reg = <0x3 0x0 0x800000>;
69 at91bootstrap@0 {
71 reg = <0x0 0x20000>;
76 reg = <0x20000 0x80000>;
81 reg = <0xa0000 0x20000>;
86 reg = <0xc0000 0x20000>;
91 reg = <0xe0000 0x280000>;
96 reg = <0x360000 0x280000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dnvidia,tegra186-gpc-dma.yaml78 reg = <0x2600000 0x210000>;
115 dma-channel-mask = <0xfffffffe>;
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-linksys-cobra.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
H A Darmada-385-linksys-caiman.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
H A Darmada-385-linksys-shelby.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
H A Darmada-xp-linksys-mamba.dts6 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
34 memory@0 {
36 reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
43 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
44 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
64 pinctrl-0 = <&ge0_rgmii_pins>;
69 bm,pool-long = <0>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch3.h12 #define CONFIG_SYS_IMMR 0x01000000
13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
15 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
21 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
23 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
24 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
[all …]
H A Dimmap_lsch2.h11 #define CONFIG_SYS_IMMR 0x01000000
12 #define CONFIG_SYS_DCSRBAR 0x20000000
13 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
14 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
16 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
17 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
18 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
19 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
20 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
21 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8976.dtsi26 #clock-cells = <0>;
32 #size-cells = <0>;
34 CPU0: cpu@0 {
37 reg = <0x0>;
48 reg = <0x1>;
59 reg = <0x2>;
70 reg = <0x3>;
81 reg = <0x100>;
92 reg = <0x101>;
103 reg = <0x102>;
[all …]
H A Dmsm8996.dtsi28 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
52 clocks = <&kryocc 0>;
67 reg = <0x0 0x1>;
71 clocks = <&kryocc 0>;
81 reg = <0x0 0x100>;
100 reg = <0x0 0x101>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
78 reg = <0x0 0x2600000 0x0 0x210000>;
116 dma-channel-mask = <0xfffffffe>;
129 ranges = <0x02900000 0x0 0x02900000 0x200000>;
134 reg = <0x02900800 0x800>;
[all …]
H A Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x0 0xf000>,
30 <0x0 0x0010f000 0x0 0x1000>;
36 reg = <0x0 0x2200000 0x0 0x10000>,
37 <0x0 0x2210000 0x0 0x10000>;
90 gpio-ranges = <&pinmux 0 0 169>;
95 reg = <0x0 0x02300000 0x0 0x1000>;
105 reg = <0x0 0x2390000 0x0 0x1000>,
106 <0x0 0x23a0000 0x0 0x1000>,
[all …]
H A Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]