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/openbmc/linux/arch/arm/mach-mv78xx0/
H A Dmv78xx0.h17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ufs/
H A Dmediatek,ufs.yaml57 reg = <0 0x11270000 0 0x2300>;
63 freq-table-hz = <0 0>;
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dfw.h7 #define FW_8192C_SIZE 0x3000
8 #define FW_8192C_START_ADDRESS 0x1000
9 #define FW_8192C_END_ADDRESS 0x3FFF
14 ((_pfwhdr->signature&0xFFFF) == 0x2300 ||\
15 (_pfwhdr->signature&0xFFFF) == 0x2301 ||\
16 (_pfwhdr->signature&0xFFFF) == 0x2302)
18 #define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0))
H A Dsw.c30 rtlpci->const_amdpci_aspm = 0; in rtl8723e_init_aspm_vars()
34 * 0 - Disable ASPM, in rtl8723e_init_aspm_vars()
44 rtlpci->const_devicepci_aspm_setting = 0x03; in rtl8723e_init_aspm_vars()
47 rtlpci->const_hostpci_aspm_setting = 0x02; in rtl8723e_init_aspm_vars()
51 * 0 - Default, in rtl8723e_init_aspm_vars()
55 * set default to RTL8192CE:0 RTL8192SE:2 in rtl8723e_init_aspm_vars()
57 rtlpci->const_hwsw_rfoff_d3 = 0; in rtl8723e_init_aspm_vars()
62 * 0 - Not support ASPM, in rtl8723e_init_aspm_vars()
74 int err = 0; in rtl8723e_init_sw_vars()
82 rtlpriv->dm.dm_flag = 0; in rtl8723e_init_sw_vars()
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_tpc0_eml_etf_regs.h23 #define mmDCORE0_TPC0_EML_ETF_RSZ 0x2004
25 #define mmDCORE0_TPC0_EML_ETF_STS 0x200C
27 #define mmDCORE0_TPC0_EML_ETF_RRD 0x2010
29 #define mmDCORE0_TPC0_EML_ETF_RRP 0x2014
31 #define mmDCORE0_TPC0_EML_ETF_RWP 0x2018
33 #define mmDCORE0_TPC0_EML_ETF_TRG 0x201C
35 #define mmDCORE0_TPC0_EML_ETF_CTL 0x2020
37 #define mmDCORE0_TPC0_EML_ETF_RWD 0x2024
39 #define mmDCORE0_TPC0_EML_ETF_MODE 0x2028
41 #define mmDCORE0_TPC0_EML_ETF_LBUFLEVEL 0x202C
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-pcie.dtsi8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da2xx_gpu.c18 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
42 OUT_RING(ring, 0x00000000); in a2xx_submit()
49 OUT_RING(ring, 0x80000000); in a2xx_submit()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
62 /* All fields present (bits 9:0) */ in a2xx_me_init()
63 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
65 OUT_RING(ring, 0x00000000); in a2xx_me_init()
67 OUT_RING(ring, 0x00000000); in a2xx_me_init()
69 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init()
70 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init()
[all …]
/openbmc/linux/drivers/regulator/
H A Dslg51000-regulator.h14 #define SLG51000_SYSCTL_PATN_ID_B0 0x1105
15 #define SLG51000_SYSCTL_PATN_ID_B1 0x1106
16 #define SLG51000_SYSCTL_PATN_ID_B2 0x1107
17 #define SLG51000_SYSCTL_SYS_CONF_A 0x1109
18 #define SLG51000_SYSCTL_SYS_CONF_D 0x110c
19 #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d
20 #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e
21 #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111
22 #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112
23 #define SLG51000_SYSCTL_FAULT_LOG1 0x1115
[all …]
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/openbmc/linux/drivers/mfd/
H A Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A Dumc-sld8.c33 static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17};
34 static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17};
35 static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44};
36 static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24};
38 {0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */
39 {0x002b0617, 0x003f0617, 0x00670617},
41 static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
42 static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac};
51 writel(0x00000000, ssif_base + 0x0000b004); in umc_start_ssif()
52 writel(0xffffffff, ssif_base + 0x0000c004); in umc_start_ssif()
[all …]
H A Dumc-pro4.c27 static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
31 writel(0x00000000, ssif_base + 0x0000b004); in umc_start_ssif()
32 writel(0xffffffff, ssif_base + 0x0000c004); in umc_start_ssif()
33 writel(0x000fffcf, ssif_base + 0x0000c008); in umc_start_ssif()
34 writel(0x00000001, ssif_base + 0x0000b000); in umc_start_ssif()
35 writel(0x00000001, ssif_base + 0x0000c000); in umc_start_ssif()
37 writel(0x03010100, ssif_base + UMC_HDMCHSEL); in umc_start_ssif()
38 writel(0x03010101, ssif_base + UMC_MDMCHSEL); in umc_start_ssif()
39 writel(0x03010100, ssif_base + UMC_DVCCHSEL); in umc_start_ssif()
40 writel(0x03010100, ssif_base + UMC_DMDCHSEL); in umc_start_ssif()
[all …]
H A Dumc-ld4.c32 static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17};
33 static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24};
35 {0x00240512, 0x00350512},
36 {0x002b0617, 0x003f0617},
38 static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
39 static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae};
48 writel(0x00000000, ssif_base + 0x0000b004); in umc_start_ssif()
49 writel(0xffffffff, ssif_base + 0x0000c004); in umc_start_ssif()
50 writel(0x000fffcf, ssif_base + 0x0000c008); in umc_start_ssif()
51 writel(0x00000001, ssif_base + 0x0000b000); in umc_start_ssif()
[all …]
/openbmc/linux/drivers/media/radio/si4713/
H A Dsi4713.h25 #define SI4713_PRODUCT_NUMBER 0x0D
41 #define SI4713_PWUP_FUNC_TX 0x02
42 #define SI4713_PWUP_FUNC_PATCH 0x0F
43 #define SI4713_PWUP_OPMOD_ANALOG 0x50
44 #define SI4713_PWUP_OPMOD_DIGITAL 0x0F
47 #define SI4713_CMD_POWER_UP 0x01
50 #define SI4713_CMD_GET_REV 0x10
53 #define SI4713_CMD_POWER_DOWN 0x11
57 #define SI4713_CMD_SET_PROPERTY 0x12
61 #define SI4713_CMD_GET_PROPERTY 0x13
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/thunder/
H A Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/openbmc/qemu/hw/usb/
H A Ddev-hub.c58 #define ClearHubFeature (0x2000 | USB_REQ_CLEAR_FEATURE)
59 #define ClearPortFeature (0x2300 | USB_REQ_CLEAR_FEATURE)
60 #define GetHubDescriptor (0xa000 | USB_REQ_GET_DESCRIPTOR)
61 #define GetHubStatus (0xa000 | USB_REQ_GET_STATUS)
62 #define GetPortStatus (0xa300 | USB_REQ_GET_STATUS)
63 #define SetHubFeature (0x2000 | USB_REQ_SET_FEATURE)
64 #define SetPortFeature (0x2300 | USB_REQ_SET_FEATURE)
66 #define PORT_STAT_CONNECTION 0x0001
67 #define PORT_STAT_ENABLE 0x0002
68 #define PORT_STAT_SUSPEND 0x0004
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/openbmc/linux/arch/powerpc/include/asm/
H A Dspu.h23 #define MFC_PUT_CMD 0x20
24 #define MFC_PUTS_CMD 0x28
25 #define MFC_PUTR_CMD 0x30
26 #define MFC_PUTF_CMD 0x22
27 #define MFC_PUTB_CMD 0x21
28 #define MFC_PUTFS_CMD 0x2A
29 #define MFC_PUTBS_CMD 0x29
30 #define MFC_PUTRF_CMD 0x32
31 #define MFC_PUTRB_CMD 0x31
32 #define MFC_PUTL_CMD 0x24
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dcik.c82 .max_level = 0,
143 return 0; in cik_query_video_codecs()
205 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_rreg()
216 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_wreg()
245 0xc200, 0xe0ffffff, 0xe0000000
250 0x31dc, 0xffffffff, 0x00000800,
251 0x31dd, 0xffffffff, 0x00000800,
252 0x31e6, 0xffffffff, 0x00007fbf,
253 0x31e7, 0xffffffff, 0x00007faf
258 0xcd5, 0x00000333, 0x00000333,
[all …]
/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop2.h15 #define VOP_FEATURE_OUTPUT_10BIT BIT(0)
17 #define WIN_FEATURE_AFBDC BIT(0)
198 #define RK3568_GRF_VO_CON1 0x0364
200 #define RK3568_REG_CFG_DONE 0x000
201 #define RK3568_VERSION_INFO 0x004
202 #define RK3568_SYS_AUTO_GATING_CTRL 0x008
203 #define RK3568_SYS_AXI_LUT_CTRL 0x024
204 #define RK3568_DSP_IF_EN 0x028
205 #define RK3568_DSP_IF_CTRL 0x02c
206 #define RK3568_DSP_IF_POL 0x030
[all …]
H A Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
H A Dcdn-dp-reg.h12 #define ADDR_IMEM 0x10000
13 #define ADDR_DMEM 0x20000
16 #define APB_CTRL 0
17 #define XT_INT_CTRL 0x04
18 #define MAILBOX_FULL_ADDR 0x08
19 #define MAILBOX_EMPTY_ADDR 0x0c
20 #define MAILBOX0_WR_DATA 0x10
21 #define MAILBOX0_RD_DATA 0x14
22 #define KEEP_ALIVE 0x18
23 #define VER_L 0x1c
[all …]
/openbmc/linux/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]
/openbmc/linux/drivers/media/usb/pwc/
H A Dpwc.h46 #define PWC_DEBUG_LEVEL_MODULE BIT(0)
74 } while (0)
86 #define PWC_TRACE(fmt, args...) do { } while(0)
87 #define PWC_DEBUG(level, fmt, args...) do { } while(0)
89 #define pwc_trace 0
97 #define FEATURE_MOTOR_PANTILT 0x0001
98 #define FEATURE_CODEC1 0x0002
99 #define FEATURE_CODEC2 0x0004
127 #define SET_LUM_CTL 0x01
128 #define GET_LUM_CTL 0x02
[all …]
/openbmc/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/openbmc/linux/drivers/scsi/
H A Dqlogicpti.h11 #define SBUS_CFG1 0x006UL
12 #define SBUS_CTRL 0x008UL
13 #define SBUS_STAT 0x00aUL
14 #define SBUS_SEMAPHORE 0x00cUL
15 #define CMD_DMA_CTRL 0x022UL
16 #define DATA_DMA_CTRL 0x042UL
17 #define MBOX0 0x080UL
18 #define MBOX1 0x082UL
19 #define MBOX2 0x084UL
20 #define MBOX3 0x086UL
[all …]

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