/openbmc/u-boot/drivers/clk/uniphier/ |
H A D | clk-uniphier-sys.c | 11 UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2) 15 UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0) 23 UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */ 24 UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */ 25 UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ 26 UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0), /* ether-phy (Pro4) */ 27 UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */ 28 UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ 29 UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */ 30 UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19), /* usb30-phy (PXs2) */ [all …]
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/openbmc/linux/drivers/clk/uniphier/ |
H A D | clk-uniphier-sys.c | 29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2) 33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2) 37 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0) 43 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2) 46 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10) 49 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8) 52 UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9) 55 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6) 58 UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch)) 62 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13) [all …]
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/openbmc/linux/sound/soc/codecs/ |
H A D | rt5514.h | 15 #define RT5514_DEVICE_ID 0x10ec5514 17 #define RT5514_RESET 0x2000 18 #define RT5514_PWR_ANA1 0x2004 19 #define RT5514_PWR_ANA2 0x2008 20 #define RT5514_I2S_CTRL1 0x2010 21 #define RT5514_I2S_CTRL2 0x2014 22 #define RT5514_VAD_CTRL6 0x2030 23 #define RT5514_EXT_VAD_CTRL 0x206c 24 #define RT5514_DIG_IO_CTRL 0x2070 25 #define RT5514_PAD_CTRL1 0x2080 [all …]
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H A D | max98396.h | 11 #define MAX98396_R2000_SW_RESET 0x2000 12 #define MAX98396_R2001_INT_RAW1 0x2001 13 #define MAX98396_R2002_INT_RAW2 0x2002 14 #define MAX98396_R2003_INT_RAW3 0x2003 15 #define MAX98396_R2004_INT_RAW4 0x2004 16 #define MAX98396_R2006_INT_STATE1 0x2006 17 #define MAX98396_R2007_INT_STATE2 0x2007 18 #define MAX98396_R2008_INT_STATE3 0x2008 19 #define MAX98396_R2009_INT_STATE4 0x2009 20 #define MAX98396_R200B_INT_FLAG1 0x200B [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/samsung/ |
H A D | samsung,exynos5433-decon.yaml | 102 reg = <0x13800000 0x2104>; 136 #size-cells = <0>; 138 port@0 { 139 reg = <0>;
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/openbmc/linux/include/video/ |
H A D | trident.h | 4 #define TRIDENTFB_DEBUG 0 20 #define CYBER9320 0x9320 21 #define CYBER9388 0x9388 22 #define CYBER9382 0x9382 /* the real PCI id for this is 9660 */ 23 #define CYBER9385 0x9385 /* ditto */ 24 #define CYBER9397 0x9397 25 #define CYBER9397DVD 0x939A 26 #define CYBER9520 0x9520 27 #define CYBER9525DVD 0x9525 28 #define TGUI9440 0x9440 [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap3-overo-common-dvi.dtsi | 13 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 14 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 15 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 16 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 17 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 18 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 19 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 20 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 21 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 22 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ [all …]
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H A D | omap3-thunder.dts | 17 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 18 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 19 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 20 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 21 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 22 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 23 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 24 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 25 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 26 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ [all …]
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H A D | omap3-ha-lcd.dts | 16 pinctrl-0 = < 29 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */ 35 OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */ 41 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 42 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 43 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 44 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 45 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 46 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 47 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ [all …]
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H A D | omap3-overo-common-lcd43.dtsi | 13 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 14 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 15 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 16 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 17 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 18 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 19 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 20 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 21 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 22 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ [all …]
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H A D | omap3-overo-common-lcd35.dtsi | 13 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 14 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 15 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 16 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 17 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 18 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 19 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 20 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 21 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 22 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ [all …]
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H A D | omap3-evm-processor-common.dtsi | 8 reg = <0x80000000 0x10000000>; /* 256 MB */ 13 pinctrl-0 = <&wl12xx_gpio>; 21 pinctrl-0 = < 29 pinctrl-0 = <&ehci_phy_pins>; 34 pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; 38 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 39 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 40 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 41 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 43 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ [all …]
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H A D | omap3-igep0020-common.dtsi | 16 pinctrl-0 = <&leds_pins>; 58 #phy-cells = <0>; 67 #size-cells = <0>; 69 port@0 { 70 reg = <0>; 105 pinctrl-0 = < 112 OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ 118 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 119 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 120 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ [all …]
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H A D | omap3-cm-t3x.dtsi | 10 reg = <0x80000000 0x10000000>; /* 256 MB */ 16 pinctrl-0 = <&green_led_pins>; 46 #phy-cells = <0>; 53 #phy-cells = <0>; 79 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 80 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 86 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 87 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 88 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 89 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ [all …]
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H A D | omap3-beagle-xm.dts | 14 cpu@0 { 21 reg = <0x80000000 0x20000000>; /* 512 MB */ 32 #clock-cells = <0>; 76 linux,code = <0x114>; 97 #phy-cells = <0>; 108 #size-cells = <0>; 110 port@0 { 111 reg = <0>; 156 reg = <0x5401b000 0x1000>; 171 reg = <0x54010000 0x1000>; [all …]
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/openbmc/linux/arch/powerpc/platforms/cell/spufs/ |
H A D | run.c | 29 case 0 : in spufs_stop_callback() 79 return 0; in spu_stopped() 122 out_be64(mfc_cntl, 0); in spu_setup_isolated() 132 (unsigned long)isolated_loader & 0xffffffff); in spu_setup_isolated() 137 ret = 0; in spu_setup_isolated() 189 ret = spu_activate(ctx, 0); in spu_run_init() 211 if (runcntl == 0) in spu_run_init() 232 ret = spu_activate(ctx, 0); in spu_run_init() 241 return 0; in spu_run_init() 247 int ret = 0; in spu_run_fini() [all …]
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/openbmc/u-boot/arch/arm/mach-uniphier/ |
H A D | sc-regs.h | 13 #define SC_BASE_ADDR 0x61840000 15 #define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110) 16 #define SC_DPLLOSCCTRL_DPLLST (0x1 << 1) 17 #define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0) 19 #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) 20 #define SC_DPLLCTRL_SSC_EN (0x1 << 31) 21 #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) 22 #define SC_DPLLCTRL_SSC_RATE (0x1 << 15) 24 #define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204) 25 #define SC_DPLLCTRL2_NRSTDS (0x1 << 28) [all …]
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/openbmc/linux/drivers/mfd/ |
H A D | si476x-prop.c | 25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array() 38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range() 49 0x0000, in si476x_core_is_valid_property_a10() 50 0x0500, 0x0501, in si476x_core_is_valid_property_a10() 51 0x0600, in si476x_core_is_valid_property_a10() 52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10() 53 0x0718, in si476x_core_is_valid_property_a10() 54 0x1207, 0x1208, in si476x_core_is_valid_property_a10() 55 0x2007, in si476x_core_is_valid_property_a10() 56 0x2300, in si476x_core_is_valid_property_a10() [all …]
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/openbmc/linux/drivers/media/radio/si4713/ |
H A D | si4713.h | 25 #define SI4713_PRODUCT_NUMBER 0x0D 41 #define SI4713_PWUP_FUNC_TX 0x02 42 #define SI4713_PWUP_FUNC_PATCH 0x0F 43 #define SI4713_PWUP_OPMOD_ANALOG 0x50 44 #define SI4713_PWUP_OPMOD_DIGITAL 0x0F 47 #define SI4713_CMD_POWER_UP 0x01 50 #define SI4713_CMD_GET_REV 0x10 53 #define SI4713_CMD_POWER_DOWN 0x11 57 #define SI4713_CMD_SET_PROPERTY 0x12 61 #define SI4713_CMD_GET_PROPERTY 0x13 [all …]
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/openbmc/linux/drivers/net/ethernet/ti/icssg/ |
H A D | icssg_switch_map.h | 21 #define FW_LINK_SPEED_1G (0x00) 22 #define FW_LINK_SPEED_100M (0x01) 23 #define FW_LINK_SPEED_10M (0x02) 24 #define FW_LINK_SPEED_HD (0x80) 29 #define FDB_AGEING_TIMEOUT_OFFSET 0x0014 32 #define HOST_PORT_DF_VLAN_OFFSET 0x001C 38 #define P1_PORT_DF_VLAN_OFFSET 0x0020 44 #define P2_PORT_DF_VLAN_OFFSET 0x0024 49 /* VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000 */ 50 #define VLAN_STATIC_REG_TABLE_OFFSET 0x0100 [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | omap3-evm-processor-common.dtsi | 8 reg = <0x80000000 0x10000000>; /* 256 MB */ 13 pinctrl-0 = <&wl12xx_gpio>; 21 pinctrl-0 = < 29 pinctrl-0 = <&ehci_phy_pins>; 34 pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; 38 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 39 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 40 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 41 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 43 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ [all …]
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H A D | omap3-igep0020-common.dtsi | 19 pinctrl-0 = <&leds_pins>; 61 #phy-cells = <0>; 70 #size-cells = <0>; 72 port@0 { 73 reg = <0>; 108 pinctrl-0 = < 115 OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ 121 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 122 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 123 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ [all …]
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H A D | omap3-beagle-xm.dts | 17 cpu@0 { 24 reg = <0x80000000 0x20000000>; /* 512 MB */ 72 linux,code = <0x114>; 93 #phy-cells = <0>; 104 #size-cells = <0>; 106 port@0 { 107 reg = <0>; 152 reg = <0x5401b000 0x1000>; 166 reg = <0x54010000 0x1000>; 181 OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ [all …]
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/openbmc/linux/drivers/media/usb/dvb-usb-v2/ |
H A D | rtl28xxu.h | 40 #define DEMOD 0x0000 41 #define USB 0x0100 42 #define SYS 0x0200 43 #define I2C 0x0300 44 #define I2C_DA 0x0600 46 #define CMD_WR_FLAG 0x0010 47 #define CMD_DEMOD_RD 0x0000 48 #define CMD_DEMOD_WR 0x0010 49 #define CMD_USB_RD 0x0100 50 #define CMD_USB_WR 0x0110 [all …]
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/openbmc/linux/sound/mips/ |
H A D | hal2.h | 15 #define H2_ISR_TSTATUS 0x01 /* RO: transaction status 1=busy */ 16 #define H2_ISR_USTATUS 0x02 /* RO: utime status bit 1=armed */ 17 #define H2_ISR_QUAD_MODE 0x04 /* codec mode 0=indigo 1=quad */ 18 #define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */ 19 #define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */ 23 #define H2_REV_AUDIO_PRESENT 0x8000 /* RO: audio present 0=present */ 24 #define H2_REV_BOARD_M 0x7000 /* RO: bits 14:12, board revision */ 25 #define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: bits 7:4, major chip revision */ 26 #define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */ 37 #define H2_IAR_TYPE_M 0xF000 /* bits 15:12, type of functional */ [all …]
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