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Searched +full:0 +full:x204000 (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/rtc/
H A Drtc-gamecube.c12 * This device sits on a bus named EXI (which is similar to SPI), channel 0,
40 #define EXICSR 0
45 #define EXICSR_DEV 0x380
46 #define EXICSR_DEV1 0x100
47 #define EXICSR_CLK 0x070
48 #define EXICSR_CLK_1MHZ 0x000
49 #define EXICSR_CLK_2MHZ 0x010
50 #define EXICSR_CLK_4MHZ 0x020
51 #define EXICSR_CLK_8MHZ 0x030
52 #define EXICSR_CLK_16MHZ 0x040
[all …]
/openbmc/linux/arch/arm/boot/dts/sigmastar/
H A Dmstar-infinity2m.dtsi28 reg = <0x1>;
36 reg = <0x204000 0x200>;
/openbmc/linux/Documentation/devicetree/bindings/arm/mstar/
H A Dmstar,smpctrl.yaml39 reg = <0x204000 0x200>;
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dda8xx-usb.txt37 channel number (0 … 3 for endpoints 1 … 4).
38 The second number is 0 for RX and 1 for TX transfers.
45 #phy-cells = <0>;
49 reg = <0x00200000 0x1000>;
58 phys = <&usb_phy 0>;
61 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
62 &cppi41dma 2 0 &cppi41dma 3 0
63 &cppi41dma 0 1 &cppi41dma 1 1
72 reg = <0x201000 0x1000
73 0x202000 0x1000
[all …]
/openbmc/qemu/include/hw/arm/
H A Draspi_platform.h67 #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
68 #define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
69 #define INTE_OFFSET 0x2000 /* VC Interrupt controller */
70 #define ST_OFFSET 0x3000 /* System Timer */
71 #define TXP_OFFSET 0x4000 /* Transposer */
72 #define JPEG_OFFSET 0x5000
73 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
74 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
75 #define ARBA_OFFSET 0x9000
76 #define BRDG_OFFSET 0xa000 /* RPiVid ASB for BCM2838 (BCM2711) */
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi16 reg = <0xc0000000 0x0>;
21 #size-cells = <0>;
23 cpu: cpu@0 {
26 reg = <0>;
78 reg = <0xfffee000 0x2000>;
84 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #clock-cells = <0>;
102 reg = <0x11800000 0x40000>,
103 <0x11e00000 0x8000>,
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dda850.dtsi20 reg = <0xc0000000 0x0>;
32 reg = <0xfffee000 0x2000>;
38 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
56 reg = <0x11800000 0x40000>,
57 <0x11e00000 0x8000>,
58 <0x11f00000 0x8000>,
59 <0x01c14044 0x4>,
60 <0x01c14174 0x8>;
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]