/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | qcom,msm8996-qmp-pcie-phy.yaml | 57 "^phy@[0-9a-f]+$": 92 const: 0 98 const: 0 130 reg = <0x34000 0x488>; 133 ranges = <0x0 0x34000 0x4000>; 149 reg = <0x1000 0x130>, 150 <0x1200 0x200>, 151 <0x1400 0x1dc>; 156 #clock-cells = <0>; 159 #phy-cells = <0>; [all …]
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/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/ |
H A D | dpu_6_4_sm6350.h | 13 .max_mixer_blendstages = 0x7, 24 .base = 0x0, .len = 0x494, 26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 28 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 29 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 30 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 37 .base = 0x1000, .len = 0x1dc, 42 .base = 0x1200, .len = 0x1dc, 47 .base = 0x1400, .len = 0x1dc, [all …]
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H A D | dpu_6_2_sc7180.h | 12 .max_mixer_blendstages = 0x9, 22 .base = 0x0, .len = 0x494, 24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 26 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 27 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 28 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 35 .base = 0x1000, .len = 0x1dc, 40 .base = 0x1200, .len = 0x1dc, 45 .base = 0x1400, .len = 0x1dc, [all …]
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/openbmc/qemu/hw/usb/ |
H A D | chipidea.c | 18 CHIPIDEA_USBx_DCIVERSION = 0x000, 19 CHIPIDEA_USBx_DCCPARAMS = 0x004, 26 return 0; in chipidea_read() 56 return 0x1; in chipidea_dc_read() 67 return 0; in chipidea_dc_read() 98 for (i = 0; i < ARRAY_SIZE(ci->iomem); i++) { in chipidea_init() 106 * Registers located between offsets 0x000 and 0xFC in chipidea_init() 110 .offset = 0x000, in chipidea_init() 111 .size = 0x100, in chipidea_init() 115 * Registers located between offsets 0x1A4 and 0x1DC in chipidea_init() [all …]
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/openbmc/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-pcs-v6_20.h | 10 #define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178 11 #define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190 12 #define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8 13 #define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc 14 #define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0 15 #define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8 16 #define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
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H A D | phy-qcom-qmp-pcs-usb-v6.h | 10 #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1 0xc4 11 #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2 0xc8 12 #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3 0xcc 13 #define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6 0xd8 14 #define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1 0xdc 15 #define QPHY_USB_V6_PCS_POWER_STATE_CONFIG1 0x90 16 #define QPHY_USB_V6_PCS_RX_SIGDET_LVL 0x188 17 #define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 18 #define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 19 #define QPHY_USB_V6_PCS_CDR_RESET_TIME 0x1b0 [all …]
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H A D | phy-qcom-qmp-pcs-v5.h | 10 #define QPHY_V5_PCS_SW_RESET 0x000 11 #define QPHY_V5_PCS_PCS_STATUS1 0x014 12 #define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040 13 #define QPHY_V5_PCS_START_CONTROL 0x044 14 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4 15 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8 16 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc 17 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8 18 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc 19 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v6_20.h | 9 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 10 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 11 #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac 12 #define QSERDES_V6_20_TX_LANE_MODE_1 0x78 13 #define QSERDES_V6_20_TX_LANE_MODE_2 0x7c 14 #define QSERDES_V6_20_TX_LANE_MODE_3 0x80 16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08 17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c 18 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20 19 #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34 [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v4_20.h | 10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 20 #define QSERDES_V4_20_RX_DFE_3 0x110 21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 [all …]
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H A D | phy-qcom-qmp-pcs-v2.h | 10 #define QPHY_V2_PCS_SW_RESET 0x000 11 #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004 12 #define QPHY_V2_PCS_START_CONTROL 0x008 13 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024 14 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028 15 #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054 16 #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058 17 #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060 18 #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064 19 #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c [all …]
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H A D | phy-qcom-qmp-pcs-v3.h | 10 #define QPHY_V3_PCS_SW_RESET 0x000 11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 12 #define QPHY_V3_PCS_START_CONTROL 0x008 13 #define QPHY_V3_PCS_TXMGN_V0 0x00c 14 #define QPHY_V3_PCS_TXMGN_V1 0x010 15 #define QPHY_V3_PCS_TXMGN_V2 0x014 16 #define QPHY_V3_PCS_TXMGN_V3 0x018 17 #define QPHY_V3_PCS_TXMGN_V4 0x01c 18 #define QPHY_V3_PCS_TXMGN_LS 0x020 19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 [all …]
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H A D | phy-qcom-qmp-pcs-v4.h | 10 #define QPHY_V4_PCS_SW_RESET 0x000 11 #define QPHY_V4_PCS_REVISION_ID0 0x004 12 #define QPHY_V4_PCS_REVISION_ID1 0x008 13 #define QPHY_V4_PCS_REVISION_ID2 0x00c 14 #define QPHY_V4_PCS_REVISION_ID3 0x010 15 #define QPHY_V4_PCS_PCS_STATUS1 0x014 16 #define QPHY_V4_PCS_PCS_STATUS2 0x018 17 #define QPHY_V4_PCS_PCS_STATUS3 0x01c 18 #define QPHY_V4_PCS_PCS_STATUS4 0x020 19 #define QPHY_V4_PCS_PCS_STATUS5 0x024 [all …]
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/openbmc/u-boot/tools/ |
H A D | kwbimage.h | 14 #define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config)) 18 #define IBR_HDR_ECC_DEFAULT 0x00 19 #define IBR_HDR_ECC_FORCED_HAMMING 0x01 20 #define IBR_HDR_ECC_FORCED_RS 0x02 21 #define IBR_HDR_ECC_DISABLED 0x03 24 #define IBR_HDR_I2C_ID 0x4D 25 #define IBR_HDR_SPI_ID 0x5A 26 #define IBR_HDR_NAND_ID 0x8B 27 #define IBR_HDR_SATA_ID 0x78 28 #define IBR_HDR_PEX_ID 0x9C [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 [all …]
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H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | dm814.h | 8 #define DM814_CLKCTRL_OFFSET 0x0 12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58) 15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150) 16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154) 17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158) 18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c) 19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160) 20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164) 21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168) 22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c) [all …]
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H A D | dm816.h | 8 #define DM816_CLKCTRL_OFFSET 0x0 12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58) 15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150) 16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154) 17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158) 18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c) 19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160) 20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164) 21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168) 22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170) [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
H A D | dram_sun8i_a23.h | 45 u32 cr; /* 0x00 */ 46 u32 ccr; /* 0x04 controller configuration register */ 47 u32 dbgcr; /* 0x08 */ 48 u8 res0[0x4]; /* 0x0c */ 49 u32 mcr0_0; /* 0x10 */ 50 u32 mcr1_0; /* 0x14 */ 51 u32 mcr0_1; /* 0x18 */ 52 u32 mcr1_1; /* 0x1c */ 53 u32 mcr0_2; /* 0x20 */ 54 u32 mcr1_2; /* 0x24 */ [all …]
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/openbmc/linux/drivers/pinctrl/ |
H A D | pinctrl-pic32.h | 12 #define ANSEL_REG 0x00 13 #define TRIS_REG 0x10 14 #define PORT_REG 0x20 15 #define LAT_REG 0x30 16 #define ODCU_REG 0x40 17 #define CNPU_REG 0x50 18 #define CNPD_REG 0x60 19 #define CNCON_REG 0x70 20 #define CNEN_REG 0x80 21 #define CNSTAT_REG 0x90 [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | dra72x-mmc-iodelay.dtsi | 37 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 38 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 39 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 40 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 41 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 42 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 48 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 49 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 50 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 51 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | dra72x-mmc-iodelay.dtsi | 45 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 46 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 47 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 48 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 49 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 50 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 56 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 57 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 58 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 59 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ [all …]
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H A D | am335x-draco.dts | 45 reg = <0x4b000000 1000000>; 53 pinctrl-0 = <&gpio_mux_pins>; 57 0x1d0 (PIN_INPUT | MUX_MODE0) /* tms jtag */ 58 0x1d4 (PIN_INPUT | MUX_MODE0) /* tdi jtag */ 59 0x1d8 (PIN_OUTPUT | MUX_MODE0) /* tdo jtag */ 60 0x1dc (PIN_INPUT | MUX_MODE0) /* tck jtag */ 61 0x1e0 (PIN_INPUT | MUX_MODE0) /* trstn jtag */ 67 0x0E8 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_plck FIX STO should be a OUTPUT driven high*/ 68 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ 69 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.mii1_txen */ [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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/openbmc/u-boot/include/dt-bindings/pinctrl/ |
H A D | pins-imx8mq.h | 24 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 25 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 26 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 27 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 28 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 29 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 30 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 31 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 32 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 33 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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