Searched +full:0 +full:x1b030000 (Results 1 – 4 of 4) sorted by relevance
39 "^jpgenc@[0-9a-f]+$":116 reg = <0 0x1a030000 0 0x10000>;121 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;129 reg = <0 0x1b030000 0 0x10000>;134 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
47 #size-cells = <0>;81 cpu0: cpu@0 {84 reg = <0x0>;91 reg = <0x100>;98 reg = <0x200>;105 reg = <0x300>;112 reg = <0x10000>;119 reg = <0x10100>;126 reg = <0x10200>;133 reg = <0x10300>;[all …]
32 /* Register Offset definitions for CMU_TOP (0x1b240000) */33 #define PLL_LOCKTIME_PLL_SHARED0 0x000034 #define PLL_LOCKTIME_PLL_SHARED1 0x000435 #define PLL_LOCKTIME_PLL_SHARED2 0x000836 #define PLL_LOCKTIME_PLL_SHARED3 0x000c37 #define PLL_LOCKTIME_PLL_SHARED4 0x001038 #define PLL_CON0_PLL_SHARED0 0x010039 #define PLL_CON3_PLL_SHARED0 0x010c40 #define PLL_CON0_PLL_SHARED1 0x014041 #define PLL_CON3_PLL_SHARED1 0x014c[all …]
51 #size-cells = <0>;53 cpu0: cpu@0 {56 reg = <0x000>;58 performance-domains = <&performance 0>;75 reg = <0x100>;77 performance-domains = <&performance 0>;94 reg = <0x200>;96 performance-domains = <&performance 0>;113 reg = <0x300>;115 performance-domains = <&performance 0>;[all …]