1*6611830fSkyrie wu# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*6611830fSkyrie wu%YAML 1.2 3*6611830fSkyrie wu--- 4*6611830fSkyrie wu$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml# 5*6611830fSkyrie wu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*6611830fSkyrie wu 7*6611830fSkyrie wutitle: MediaTek JPEG Encoder 8*6611830fSkyrie wu 9*6611830fSkyrie wumaintainers: 10*6611830fSkyrie wu - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com> 11*6611830fSkyrie wu 12*6611830fSkyrie wudescription: 13*6611830fSkyrie wu MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs 14*6611830fSkyrie wu 15*6611830fSkyrie wuproperties: 16*6611830fSkyrie wu compatible: 17*6611830fSkyrie wu const: mediatek,mt8195-jpgenc 18*6611830fSkyrie wu 19*6611830fSkyrie wu power-domains: 20*6611830fSkyrie wu maxItems: 1 21*6611830fSkyrie wu 22*6611830fSkyrie wu iommus: 23*6611830fSkyrie wu maxItems: 4 24*6611830fSkyrie wu description: 25*6611830fSkyrie wu Points to the respective IOMMU block with master port as argument, see 26*6611830fSkyrie wu Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. 27*6611830fSkyrie wu Ports are according to the HW. 28*6611830fSkyrie wu 29*6611830fSkyrie wu "#address-cells": 30*6611830fSkyrie wu const: 2 31*6611830fSkyrie wu 32*6611830fSkyrie wu "#size-cells": 33*6611830fSkyrie wu const: 2 34*6611830fSkyrie wu 35*6611830fSkyrie wu ranges: true 36*6611830fSkyrie wu 37*6611830fSkyrie wu# Required child node: 38*6611830fSkyrie wupatternProperties: 39*6611830fSkyrie wu "^jpgenc@[0-9a-f]+$": 40*6611830fSkyrie wu type: object 41*6611830fSkyrie wu description: 42*6611830fSkyrie wu The jpeg encoder hardware device node which should be added as subnodes to 43*6611830fSkyrie wu the main jpeg node. 44*6611830fSkyrie wu 45*6611830fSkyrie wu properties: 46*6611830fSkyrie wu compatible: 47*6611830fSkyrie wu const: mediatek,mt8195-jpgenc-hw 48*6611830fSkyrie wu 49*6611830fSkyrie wu reg: 50*6611830fSkyrie wu maxItems: 1 51*6611830fSkyrie wu 52*6611830fSkyrie wu iommus: 53*6611830fSkyrie wu minItems: 1 54*6611830fSkyrie wu maxItems: 32 55*6611830fSkyrie wu description: 56*6611830fSkyrie wu List of the hardware port in respective IOMMU block for current Socs. 57*6611830fSkyrie wu Refer to bindings/iommu/mediatek,iommu.yaml. 58*6611830fSkyrie wu 59*6611830fSkyrie wu interrupts: 60*6611830fSkyrie wu maxItems: 1 61*6611830fSkyrie wu 62*6611830fSkyrie wu clocks: 63*6611830fSkyrie wu maxItems: 1 64*6611830fSkyrie wu 65*6611830fSkyrie wu clock-names: 66*6611830fSkyrie wu items: 67*6611830fSkyrie wu - const: jpgenc 68*6611830fSkyrie wu 69*6611830fSkyrie wu power-domains: 70*6611830fSkyrie wu maxItems: 1 71*6611830fSkyrie wu 72*6611830fSkyrie wu required: 73*6611830fSkyrie wu - compatible 74*6611830fSkyrie wu - reg 75*6611830fSkyrie wu - iommus 76*6611830fSkyrie wu - interrupts 77*6611830fSkyrie wu - clocks 78*6611830fSkyrie wu - clock-names 79*6611830fSkyrie wu - power-domains 80*6611830fSkyrie wu 81*6611830fSkyrie wu additionalProperties: false 82*6611830fSkyrie wu 83*6611830fSkyrie wurequired: 84*6611830fSkyrie wu - compatible 85*6611830fSkyrie wu - power-domains 86*6611830fSkyrie wu - iommus 87*6611830fSkyrie wu - ranges 88*6611830fSkyrie wu 89*6611830fSkyrie wuadditionalProperties: false 90*6611830fSkyrie wu 91*6611830fSkyrie wuexamples: 92*6611830fSkyrie wu - | 93*6611830fSkyrie wu #include <dt-bindings/interrupt-controller/arm-gic.h> 94*6611830fSkyrie wu #include <dt-bindings/memory/mt8195-memory-port.h> 95*6611830fSkyrie wu #include <dt-bindings/interrupt-controller/irq.h> 96*6611830fSkyrie wu #include <dt-bindings/clock/mt8195-clk.h> 97*6611830fSkyrie wu #include <dt-bindings/power/mt8195-power.h> 98*6611830fSkyrie wu 99*6611830fSkyrie wu soc { 100*6611830fSkyrie wu #address-cells = <2>; 101*6611830fSkyrie wu #size-cells = <2>; 102*6611830fSkyrie wu 103*6611830fSkyrie wu jpgenc-master { 104*6611830fSkyrie wu compatible = "mediatek,mt8195-jpgenc"; 105*6611830fSkyrie wu power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 106*6611830fSkyrie wu iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 107*6611830fSkyrie wu <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 108*6611830fSkyrie wu <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 109*6611830fSkyrie wu <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 110*6611830fSkyrie wu #address-cells = <2>; 111*6611830fSkyrie wu #size-cells = <2>; 112*6611830fSkyrie wu ranges; 113*6611830fSkyrie wu 114*6611830fSkyrie wu jpgenc@1a030000 { 115*6611830fSkyrie wu compatible = "mediatek,mt8195-jpgenc-hw"; 116*6611830fSkyrie wu reg = <0 0x1a030000 0 0x10000>; 117*6611830fSkyrie wu iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 118*6611830fSkyrie wu <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 119*6611830fSkyrie wu <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 120*6611830fSkyrie wu <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 121*6611830fSkyrie wu interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 122*6611830fSkyrie wu clocks = <&vencsys CLK_VENC_JPGENC>; 123*6611830fSkyrie wu clock-names = "jpgenc"; 124*6611830fSkyrie wu power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 125*6611830fSkyrie wu }; 126*6611830fSkyrie wu 127*6611830fSkyrie wu jpgenc@1b030000 { 128*6611830fSkyrie wu compatible = "mediatek,mt8195-jpgenc-hw"; 129*6611830fSkyrie wu reg = <0 0x1b030000 0 0x10000>; 130*6611830fSkyrie wu iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 131*6611830fSkyrie wu <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 132*6611830fSkyrie wu <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 133*6611830fSkyrie wu <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 134*6611830fSkyrie wu interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 135*6611830fSkyrie wu clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 136*6611830fSkyrie wu clock-names = "jpgenc"; 137*6611830fSkyrie wu power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 138*6611830fSkyrie wu }; 139*6611830fSkyrie wu }; 140*6611830fSkyrie wu }; 141