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12

/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dqcom,ebi2.txt24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
58 ranges = <0 0x0 0x1a800000 0x00800000>,
59 <1 0x0 0x1b000000 0x00800000>,
60 <2 0x0 0x1b800000 0x00800000>,
61 <3 0x0 0x1d000000 0x08000000>,
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h22 #define AR71XX_APB_BASE 0x18000000
23 #define AR71XX_GE0_BASE 0x19000000
24 #define AR71XX_GE0_SIZE 0x10000
25 #define AR71XX_GE1_BASE 0x1a000000
26 #define AR71XX_GE1_SIZE 0x10000
27 #define AR71XX_EHCI_BASE 0x1b000000
28 #define AR71XX_EHCI_SIZE 0x1000
29 #define AR71XX_OHCI_BASE 0x1c000000
30 #define AR71XX_OHCI_SIZE 0x1000
31 #define AR71XX_SPI_BASE 0x1f000000
[all …]
/openbmc/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h19 #define AR71XX_APB_BASE 0x18000000
20 #define AR71XX_GE0_BASE 0x19000000
21 #define AR71XX_GE0_SIZE 0x10000
22 #define AR71XX_GE1_BASE 0x1a000000
23 #define AR71XX_GE1_SIZE 0x10000
24 #define AR71XX_EHCI_BASE 0x1b000000
25 #define AR71XX_EHCI_SIZE 0x1000
26 #define AR71XX_OHCI_BASE 0x1c000000
27 #define AR71XX_OHCI_SIZE 0x1000
28 #define AR71XX_SPI_BASE 0x1f000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,ipesys.txt20 reg = <0 0x1b000000 0 0x1000>;
H A Dmediatek,ethsys.txt26 reg = <0 0x1b000000 0 0x1000>;
H A Dmediatek,mt8192-clock.yaml56 reg = <0x10720000 0x1000>;
63 reg = <0x11007000 0x1000>;
70 reg = <0x11cb1000 0x1000>;
77 reg = <0x11d03000 0x1000>;
84 reg = <0x11d23000 0x1000>;
91 reg = <0x11e01000 0x1000>;
98 reg = <0x11f02000 0x1000>;
105 reg = <0x11f10000 0x1000>;
112 reg = <0x13fbf000 0x1000>;
119 reg = <0x15020000 0x1000>;
[all …]
H A Dmediatek,mt8195-clock.yaml68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
124 reg = <0x15110000 0x1000>;
131 reg = <0x15130000 0x1000>;
[all …]
/openbmc/u-boot/arch/mips/include/asm/
H A Dmalta.h10 #define MALTA_GT_BASE 0x1be00000
11 #define MALTA_GT_PCIIO_BASE 0x18000000
12 #define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8)
14 #define MALTA_MSC01_BIU_BASE 0x1bc80000
15 #define MALTA_MSC01_PCI_BASE 0x1bd00000
16 #define MALTA_MSC01_PBC_BASE 0x1bd40000
17 #define MALTA_MSC01_IP1_BASE 0x1bc00000
18 #define MALTA_MSC01_IP1_SIZE 0x00400000
19 #define MALTA_MSC01_IP2_BASE1 0x10000000
20 #define MALTA_MSC01_IP2_SIZE1 0x08000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dapm-xgene-dma.txt27 clocks = <&socplldiv2 0>;
28 reg = <0x0 0x1f27c000 0x0 0x1000>;
36 reg = <0x0 0x1f270000 0x0 0x10000>,
37 <0x0 0x1f200000 0x0 0x10000>,
38 <0x0 0x1b000000 0x0 0x400000>,
39 <0x0 0x1054a000 0x0 0x100>;
40 interrupts = <0x0 0x82 0x4>,
41 <0x0 0xb8 0x4>,
42 <0x0 0xb9 0x4>,
43 <0x0 0xba 0x4>,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dingenic,nemc.yaml14 pattern: "^memory-controller@[0-9a-f]+$"
40 ".*@[0-9]+$":
60 reg = <0x13410000 0x10000>;
63 ranges = <1 0 0x1b000000 0x1000000>,
64 <2 0 0x1a000000 0x1000000>,
65 <3 0 0x19000000 0x1000000>,
66 <4 0 0x18000000 0x1000000>,
67 <5 0 0x17000000 0x1000000>,
68 <6 0 0x16000000 0x1000000>;
77 pinctrl-0 = <&pins_nemc_cs6>;
[all …]
/openbmc/linux/arch/powerpc/crypto/
H A Daesp10-ppc.pl103 $LITTLE_ENDIAN = ($flavour=~/le$/) ? $SIZE_T : 0;
105 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
121 my ($zero,$in0,$in1,$key,$rcon,$mask,$tmp)=map("v$_",(0..6));
131 .long 0x01000000, 0x01000000, 0x01000000, 0x01000000 ?rev
132 .long 0x1b000000, 0x1b000000, 0x1b000000, 0x1b000000 ?rev
133 .long 0x0d0e0f0c, 0x0d0e0f0c, 0x0d0e0f0c, 0x0d0e0f0c ?rev
134 .long 0,0,0,0 ?asis
139 addi $ptr,$ptr,-0x48
142 .long 0
143 .byte 0,12,0x14,0,0,0,0,0
[all …]
/openbmc/linux/arch/arm/configs/
H A Dlpc18xx_defconfig21 CONFIG_DRAM_BASE=0x28000000
22 CONFIG_DRAM_SIZE=0x02000000
23 CONFIG_FLASH_MEM_BASE=0x1b000000
24 CONFIG_FLASH_SIZE=0x00080000
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dingenic,nand.yaml66 reg = <0x13410000 0x10000>;
69 ranges = <1 0 0x1b000000 0x1000000>,
70 <2 0 0x1a000000 0x1000000>,
71 <3 0 0x19000000 0x1000000>,
72 <4 0 0x18000000 0x1000000>,
73 <5 0 0x17000000 0x1000000>,
74 <6 0 0x16000000 0x1000000>;
80 reg = <1 0 0x1000000>;
83 #size-cells = <0>;
94 pinctrl-0 = <&pins_nemc>;
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Djz4780.dtsi11 #address-cells = <0>;
19 reg = <0x10001000 0x50>;
30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 reg = <0x10000000 0x100>;
51 reg = <0x13450000 0x1000>;
61 reg = <0x13460000 0x1000>;
71 reg = <0x10030000 0x100>;
85 reg = <0x10031000 0x100>;
99 reg = <0x10032000 0x100>;
[all …]
/openbmc/linux/arch/arc/boot/dts/
H A Daxc001.dtsi23 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
26 #clock-cells = <0>;
32 #clock-cells = <0>;
49 reg = < 0x2000 0x80 >;
51 #size-cells = <0>;
53 ictl_intc: gpio-controller@0 {
58 reg = <0>;
68 reg = <0x5000 0x100>;
97 reg = < 0x0 0xe0012000 0x0 0x200 >;
106 reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
[all …]
/openbmc/linux/arch/mips/alchemy/devboards/
H A Ddb1000.c49 return 0; in db1000_board_setup()
56 if ((slot < 12) || (slot > 13) || pin == 0) in db1500_map_pci_irq()
59 return (pin == 1) ? AU1500_PCI_INTA : 0xff; in db1500_map_pci_irq()
74 [0] = {
76 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
88 .id = 0,
99 [0] = {
101 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
113 .id = 0,
123 [0] = {
[all …]
/openbmc/linux/arch/mips/boot/dts/qca/
H A Dar9331.dtsi12 #size-cells = <0>;
14 cpu@0 {
18 reg = <0>;
34 #clock-cells = <0>;
57 reg = <0x18000000 0x100>;
64 reg = <0x18020000 0x14>;
76 reg = <0x18040000 0x34>;
92 reg = <0x18050000 0x100>;
102 reg = <0x18060010 0x8>;
113 reg = <0x1806001c 0x4>;
[all …]
/openbmc/u-boot/drivers/soc/keystone/
H A Dkeystone_serdes.c13 #define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x)))
14 #define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
15 #define SERDES_COMLANE_REGS 0x0a00
16 #define SERDES_WIZ_REGS 0x1fc0
18 #define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
19 #define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
20 #define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
21 #define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
22 #define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
23 #define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6779.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x000>;
39 reg = <0x100>;
46 reg = <0x200>;
53 reg = <0x300>;
60 reg = <0x400>;
67 reg = <0x500>;
74 reg = <0x600>;
81 reg = <0x700>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dmt7623.dtsi24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
40 reg = <0x1>;
50 reg = <0x2>;
60 reg = <0x3>;
71 #clock-cells = <0>;
76 #clock-cells = <0>;
81 clk26m: oscillator-0 {
83 #clock-cells = <0>;
[all …]
H A Dmt7629.dtsi24 #size-cells = <0>;
27 cpu@0 {
30 reg = <0x0>;
37 reg = <0x1>;
42 clk20m: oscillator@0 {
44 #clock-cells = <0>;
51 #clock-cells = <0>;
69 reg = <0x10000000 0x1000>;
76 reg = <0x10002000 0x1000>;
83 reg = <0x10004000 0x80>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/apm/
H A Dapm-storm.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
29 reg = <0x0 0x001>;
31 cpu-release-addr = <0x1 0x0000fff8>;
37 reg = <0x0 0x100>;
39 cpu-release-addr = <0x1 0x0000fff8>;
45 reg = <0x0 0x101>;
47 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/openbmc/linux/arch/mips/sni/
H A Drm200.c37 MEMPORT(0x160003f8, RM200_I8259A_IRQ_BASE + 4),
38 MEMPORT(0x160002f8, RM200_I8259A_IRQ_BASE + 3),
52 .start = 0x1cd41ffc,
53 .end = 0x1cd41fff,
66 .start = 0x18000000,
67 .end = 0x180fffff,
71 .start = 0x1b000000,
72 .end = 0x1b000004,
76 .start = 0x1ff00000,
77 .end = 0x1ff00020,
[all …]
/openbmc/u-boot/arch/x86/dts/microcode/
H A Dm12306a9_0000001b.dtsi37 intel,update-revision = <0x1b>;
38 intel,date-code = <0x5292014>;
39 intel,processor-signature = <0x306a9>;
40 intel,checksum = <0x579ae07a>;
42 intel,processor-flags = <0x12>;
46 0x01000000 0x1b000000 0x14202905 0xa9060300
47 0x7ae09a57 0x01000000 0x12000000 0xd02f0000
48 0x00300000 0x00000000 0x00000000 0x00000000
49 0x00000000 0xa1000000 0x01000200 0x1b000000
50 0x00000000 0x00000000 0x16051420 0x610b0000
[all …]

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