1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 2556cc1c5SAlexey Brodkin/* 3556cc1c5SAlexey Brodkin * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 4556cc1c5SAlexey Brodkin */ 5556cc1c5SAlexey Brodkin 6556cc1c5SAlexey Brodkin/* 7556cc1c5SAlexey Brodkin * Device tree for AXC001 770D/EM6/AS221 CPU card 8556cc1c5SAlexey Brodkin * Note that this file only supports the 770D CPU 9556cc1c5SAlexey Brodkin */ 10556cc1c5SAlexey Brodkin 112e8cd938SVineet Gupta/include/ "skeleton.dtsi" 122e8cd938SVineet Gupta 13556cc1c5SAlexey Brodkin/ { 14556cc1c5SAlexey Brodkin compatible = "snps,arc"; 15f862b315SEugeniy Paltsev #address-cells = <2>; 16f862b315SEugeniy Paltsev #size-cells = <2>; 17556cc1c5SAlexey Brodkin 18556cc1c5SAlexey Brodkin cpu_card { 19556cc1c5SAlexey Brodkin compatible = "simple-bus"; 20556cc1c5SAlexey Brodkin #address-cells = <1>; 21556cc1c5SAlexey Brodkin #size-cells = <1>; 22556cc1c5SAlexey Brodkin 23f862b315SEugeniy Paltsev ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 24556cc1c5SAlexey Brodkin 25b3d6aba8SVineet Gupta core_clk: core_clk { 26b3d6aba8SVineet Gupta #clock-cells = <0>; 27b3d6aba8SVineet Gupta compatible = "fixed-clock"; 28b3d6aba8SVineet Gupta clock-frequency = <750000000>; 29b3d6aba8SVineet Gupta }; 30b3d6aba8SVineet Gupta 3193c53f23SEugeniy Paltsev input_clk: input-clk { 3293c53f23SEugeniy Paltsev #clock-cells = <0>; 3393c53f23SEugeniy Paltsev compatible = "fixed-clock"; 3493c53f23SEugeniy Paltsev clock-frequency = <33333333>; 3593c53f23SEugeniy Paltsev }; 3693c53f23SEugeniy Paltsev 379ba7648cSVineet Gupta core_intc: arc700-intc@cpu { 38556cc1c5SAlexey Brodkin compatible = "snps,arc700-intc"; 39556cc1c5SAlexey Brodkin interrupt-controller; 40556cc1c5SAlexey Brodkin #interrupt-cells = <1>; 41556cc1c5SAlexey Brodkin }; 42556cc1c5SAlexey Brodkin 43556cc1c5SAlexey Brodkin /* 44556cc1c5SAlexey Brodkin * this GPIO block ORs all interrupts on CPU card (creg,..) 45556cc1c5SAlexey Brodkin * to uplink only 1 IRQ to ARC core intc 46556cc1c5SAlexey Brodkin */ 47ef4c54c3SAlexey Brodkin dw-apb-gpio@2000 { 48556cc1c5SAlexey Brodkin compatible = "snps,dw-apb-gpio"; 49556cc1c5SAlexey Brodkin reg = < 0x2000 0x80 >; 50556cc1c5SAlexey Brodkin #address-cells = <1>; 51556cc1c5SAlexey Brodkin #size-cells = <0>; 52556cc1c5SAlexey Brodkin 53556cc1c5SAlexey Brodkin ictl_intc: gpio-controller@0 { 54556cc1c5SAlexey Brodkin compatible = "snps,dw-apb-gpio-port"; 55556cc1c5SAlexey Brodkin gpio-controller; 56556cc1c5SAlexey Brodkin #gpio-cells = <2>; 57556cc1c5SAlexey Brodkin snps,nr-gpios = <30>; 58556cc1c5SAlexey Brodkin reg = <0>; 59556cc1c5SAlexey Brodkin interrupt-controller; 60556cc1c5SAlexey Brodkin #interrupt-cells = <2>; 619ba7648cSVineet Gupta interrupt-parent = <&core_intc>; 62556cc1c5SAlexey Brodkin interrupts = <15>; 63556cc1c5SAlexey Brodkin }; 64556cc1c5SAlexey Brodkin }; 65556cc1c5SAlexey Brodkin 66ef4c54c3SAlexey Brodkin debug_uart: dw-apb-uart@5000 { 67556cc1c5SAlexey Brodkin compatible = "snps,dw-apb-uart"; 68556cc1c5SAlexey Brodkin reg = <0x5000 0x100>; 69556cc1c5SAlexey Brodkin clock-frequency = <33333000>; 70556cc1c5SAlexey Brodkin interrupt-parent = <&ictl_intc>; 71556cc1c5SAlexey Brodkin interrupts = <19 4>; 72556cc1c5SAlexey Brodkin baud = <115200>; 73556cc1c5SAlexey Brodkin reg-shift = <2>; 74556cc1c5SAlexey Brodkin reg-io-width = <4>; 75556cc1c5SAlexey Brodkin }; 76556cc1c5SAlexey Brodkin 776227e9f0SAlexey Brodkin arcpct0: pct { 78556cc1c5SAlexey Brodkin compatible = "snps,arc700-pct"; 79556cc1c5SAlexey Brodkin }; 80556cc1c5SAlexey Brodkin }; 81556cc1c5SAlexey Brodkin 82e0183f52SAlexey Brodkin /* 83e0183f52SAlexey Brodkin * This INTC is actually connected to DW APB GPIO 84e0183f52SAlexey Brodkin * which acts as a wire between MB INTC and CPU INTC. 85e0183f52SAlexey Brodkin * GPIO INTC is configured in platform init code 86e0183f52SAlexey Brodkin * and here we mimic direct connection from MB INTC to 87e0183f52SAlexey Brodkin * CPU INTC, thus we set "interrupts = <7>" instead of 88e0183f52SAlexey Brodkin * "interrupts = <12>" 89e0183f52SAlexey Brodkin * 90e0183f52SAlexey Brodkin * This intc actually resides on MB, but we move it here to 91e0183f52SAlexey Brodkin * avoid duplicating the MB dtsi file given that IRQ from 92e0183f52SAlexey Brodkin * this intc to cpu intc are different for axs101 and axs103 93e0183f52SAlexey Brodkin */ 94*05b1be68SZhen Lei mb_intc: interrupt-controller@e0012000 { 95e0183f52SAlexey Brodkin #interrupt-cells = <1>; 96e0183f52SAlexey Brodkin compatible = "snps,dw-apb-ictl"; 97f862b315SEugeniy Paltsev reg = < 0x0 0xe0012000 0x0 0x200 >; 98e0183f52SAlexey Brodkin interrupt-controller; 999ba7648cSVineet Gupta interrupt-parent = <&core_intc>; 100e0183f52SAlexey Brodkin interrupts = < 7 >; 101e0183f52SAlexey Brodkin }; 102e0183f52SAlexey Brodkin 103556cc1c5SAlexey Brodkin memory { 104556cc1c5SAlexey Brodkin device_type = "memory"; 1059ed68785SEugeniy Paltsev /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ 106f862b315SEugeniy Paltsev reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */ 107cb2ad5e5SAlexey Brodkin }; 108cb2ad5e5SAlexey Brodkin 109cb2ad5e5SAlexey Brodkin reserved-memory { 110f862b315SEugeniy Paltsev #address-cells = <2>; 111f862b315SEugeniy Paltsev #size-cells = <2>; 112cb2ad5e5SAlexey Brodkin ranges; 113cb2ad5e5SAlexey Brodkin /* 114cb2ad5e5SAlexey Brodkin * We just move frame buffer area to the very end of 115cb2ad5e5SAlexey Brodkin * available DDR. And even though in case of ARC770 there's 116cb2ad5e5SAlexey Brodkin * no strict requirement for a frame-buffer to be in any 117cb2ad5e5SAlexey Brodkin * particular location it allows us to use the same 118cb2ad5e5SAlexey Brodkin * base board's DT node for ARC PGU as for ARc HS38. 119cb2ad5e5SAlexey Brodkin */ 120cb2ad5e5SAlexey Brodkin frame_buffer: frame_buffer@9e000000 { 121cb2ad5e5SAlexey Brodkin compatible = "shared-dma-pool"; 122f862b315SEugeniy Paltsev reg = <0x0 0x9e000000 0x0 0x2000000>; 123cb2ad5e5SAlexey Brodkin no-map; 124cb2ad5e5SAlexey Brodkin }; 125556cc1c5SAlexey Brodkin }; 126556cc1c5SAlexey Brodkin}; 127