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/openbmc/u-boot/board/topic/zynq/zynq-topic-miamiplus/
H A Dps7_regs.txt1 0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz)
2 0xf8000700 0x1202 // MIO configuration
3 0xf8000704 0x1202
4 0xf8000708 0x202
5 0xf800070c 0x202
6 0xf8000710 0x202
7 0xf8000714 0x202
8 0xf8000718 0x202
9 0xf800071c 0x200
10 0xf8000720 0x202
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/panel/
H A Dleadtek,ltk500hd1829.yaml7 title: Leadtek LTK500HD1829 5.0in 720x1280 DSI panel
39 #size-cells = <0>;
41 panel@0 {
43 reg = <0>;
H A Dleadtek,ltk050h3146w.yaml7 title: Leadtek LTK050H3146W 5.0in 720x1280 DSI panel
41 #size-cells = <0>;
42 panel@0 {
44 reg = <0>;
H A Draydium,rm68200.yaml13 The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD
47 #size-cells = <0>;
48 panel@0 {
50 reg = <0>;
51 reset-gpios = <&gpiof 15 0>;
H A Dxinpeng,xpp055c272.yaml7 title: Xinpeng XPP055C272 5.5in 720x1280 DSI panel
41 #size-cells = <0>;
43 panel@0 {
45 reg = <0>;
/openbmc/linux/drivers/firmware/efi/
H A Dsysfb_efi.c30 OVERRIDE_NONE = 0x0,
31 OVERRIDE_BASE = 0x1,
32 OVERRIDE_STRIDE = 0x2,
33 OVERRIDE_HEIGHT = 0x4,
34 OVERRIDE_WIDTH = 0x8,
38 [M_I17] = { "i17", 0x80010000, 1472 * 4, 1440, 900, OVERRIDE_NONE },
39 [M_I20] = { "i20", 0x80010000, 1728 * 4, 1680, 1050, OVERRIDE_NONE }, /* guess */
40 [M_I20_SR] = { "imac7", 0x40010000, 1728 * 4, 1680, 1050, OVERRIDE_NONE },
41 [M_I24] = { "i24", 0x80010000, 2048 * 4, 1920, 1200, OVERRIDE_NONE }, /* guess */
42 [M_I24_8_1] = { "imac8", 0xc0060000, 2048 * 4, 1920, 1200, OVERRIDE_NONE },
[all …]
/openbmc/linux/include/linux/soc/samsung/
H A Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/openbmc/linux/include/uapi/linux/
H A Dcycx_cfm.h28 #define CFM_IMAGE_SIZE 0x20000 /* max size of CYCX code image file */
31 #define CFM_LOAD_BUFSZ 0x400 /* buffer size for reset code (buffer_load) */
34 #define GEN_POWER_ON 0x1280
36 #define GEN_SET_SEG 0x1401 /* boot segment setting. */
37 #define GEN_BOOT_DAT 0x1402 /* boot data. */
38 #define GEN_START 0x1403 /* board start. */
39 #define GEN_DEFPAR 0x1404 /* buffer length for boot. */
/openbmc/linux/sound/soc/mediatek/mt2701/
H A Dmt2701-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON4 0x0010
14 #define AUDIO_TOP_CON5 0x0014
15 #define AFE_DAIBT_CON0 0x001c
16 #define AFE_MRGIF_CON 0x003c
17 #define ASMI_TIMING_CON1 0x0100
18 #define ASMO_TIMING_CON1 0x0104
19 #define PWR1_ASM_CON1 0x0108
20 #define ASYS_TOP_CON 0x0600
21 #define ASYS_I2SIN1_CON 0x0604
[all …]
/openbmc/linux/drivers/irqchip/
H A Dirq-clps711x.c19 #define CLPS711X_INTSR1 (0x0240)
20 #define CLPS711X_INTMR1 (0x0280)
21 #define CLPS711X_BLEOI (0x0600)
22 #define CLPS711X_MCEOI (0x0640)
23 #define CLPS711X_TEOI (0x0680)
24 #define CLPS711X_TC1EOI (0x06c0)
25 #define CLPS711X_TC2EOI (0x0700)
26 #define CLPS711X_RTCEOI (0x0740)
27 #define CLPS711X_UMSEOI (0x0780)
28 #define CLPS711X_COEOI (0x07c0)
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/thunder/
H A Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/openbmc/linux/drivers/video/backlight/
H A Dotm3225a.c22 #define OTM3225A_INDEX_REG 0x70
23 #define OTM3225A_DATA_REG 0x72
26 #define DRIVER_OUTPUT_CTRL_1 0x01
27 #define DRIVER_WAVEFORM_CTRL 0x02
28 #define ENTRY_MODE 0x03
29 #define SCALING_CTRL 0x04
30 #define DISPLAY_CTRL_1 0x07
31 #define DISPLAY_CTRL_2 0x08
32 #define DISPLAY_CTRL_3 0x09
33 #define FRAME_CYCLE_CTRL 0x0A
[all …]
/openbmc/linux/arch/s390/include/asm/
H A Dlowcore.h25 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
26 __u32 ipl_parmblock_ptr; /* 0x0014 */
27 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
28 __u32 ext_params; /* 0x0080 */
31 __u16 ext_cpu_addr; /* 0x0084 */
32 __u16 ext_int_code; /* 0x0086 */
36 __u32 svc_int_code; /* 0x0088 */
39 __u16 pgm_ilc; /* 0x008c */
40 __u16 pgm_code; /* 0x008e */
44 __u32 data_exc_code; /* 0x0090 */
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dotx2_reg.h14 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
15 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
16 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
17 #define RVU_PF_VF_BAR4_ADDR (0x10)
18 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
19 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
20 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
21 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
22 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
23 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
[all …]
/openbmc/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-reg.h13 #define HOST_REGISTER1 0x0000
14 #define HOST_REGISTER2 0x0001
17 #define CHIP_CTRL 0x0100
18 #define AFE_AB_CTRL 0x0104
19 #define AFE_CD_CTRL 0x0108
20 #define AFE_EF_CTRL 0x010C
21 #define AFE_GH_CTRL 0x0110
22 #define DENC_AB_CTRL 0x0114
23 #define BYP_AB_CTRL 0x0118
24 #define MON_A_CTRL 0x011C
[all …]
/openbmc/linux/drivers/gpu/drm/loongson/
H A Dlsdc_regs.h24 #define LS7A1000_PIXPLL0_REG 0x04B0
25 #define LS7A1000_PIXPLL1_REG 0x04C0
28 #define LS7A1000_PLL_GFX_REG 0x0490
30 #define LS7A1000_CONF_REG_BASE 0x10010000
34 #define LS7A2000_PIXPLL0_REG 0x04B0
35 #define LS7A2000_PIXPLL1_REG 0x04C0
38 #define LS7A2000_PLL_GFX_REG 0x0490
40 #define LS7A2000_CONF_REG_BASE 0x10010000
43 #define CFG_PIX_FMT_MASK GENMASK(2, 0)
46 LSDC_PF_NONE = 0,
[all …]
/openbmc/qemu/docs/specs/
H A Dppc-spapr-xive.rst199 - ``0x0000 .. 0x0FFF`` 4K CPU IPIs (only used under XIVE)
200 - ``0x1000 .. 0x1000`` 1 EPOW
201 - ``0x1001 .. 0x1001`` 1 HOTPLUG
202 - ``0x1002 .. 0x10FF`` unused
203 - ``0x1100 .. 0x11FF`` 256 VIO devices
204 - ``0x1200 .. 0x127F`` 32x4 LSIs for PHB devices
205 - ``0x1280 .. 0x12FF`` unused
206 - ``0x1300 .. 0x1FFF`` PHB MSIs (dynamically allocated)
238 00000000 MSI -- 00000010 0/6 380/16384 @1fe3e0000 ^1 [ 80000010 ... ]
246 00001000 MSI -- 00000012 0/6 380/16384 @1fe3e0000 ^1 [ 80000010 ... ]
[all …]
/openbmc/qemu/target/s390x/
H A Ds390x-internal.h19 uint32_t ccw1[2]; /* 0x000 */
20 uint32_t ccw2[4]; /* 0x008 */
21 uint8_t pad1[0x80 - 0x18]; /* 0x018 */
22 uint32_t ext_params; /* 0x080 */
23 uint16_t cpu_addr; /* 0x084 */
24 uint16_t ext_int_code; /* 0x086 */
25 uint16_t svc_ilen; /* 0x088 */
26 uint16_t svc_code; /* 0x08a */
27 uint16_t pgm_ilen; /* 0x08c */
28 uint16_t pgm_code; /* 0x08e */
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx93.c58 { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
59 { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
60 { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL },
61 { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
62 { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
63 { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
64 { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
65 { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, },
66 { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, },
67 { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, },
[all …]
/openbmc/qemu/hw/misc/
H A Dexynos4210_pmu.c35 #define DEBUG_PMU 0
39 #define DEBUG_PMU_EXTEND 0
46 } while (0)
52 } while (0)
54 #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0)
58 #define PRINT_DEBUG(fmt, args...) do {} while (0)
59 #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0)
65 #define OM_STAT 0x0000 /* OM status register */
66 #define RTC_CLKO_SEL 0x000C /* Controls RTCCLKOUT */
67 #define GNSS_RTC_OUT_CTRL 0x0010 /* Controls GNSS_RTC_OUT */
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Dpci.h10 #define MDIO_PG0_G1 0
14 #define RAC_CTRL_PPR 0x00
15 #define RAC_ANA0A 0x0A
17 #define RAC_ANA0C 0x0C
19 #define RAC_ANA10 0x10
21 #define RAC_REG_REV2 0x1B
23 #define PCIE_DPHY_DLY_25US 0x1
24 #define RAC_ANA19 0x19
26 #define RAC_REG_FLD_0 0x1D
28 #define PCIE_AUTOK_4 0x3
[all …]
/openbmc/linux/drivers/net/ethernet/renesas/
H A Drswitch.h17 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \
23 for (i--; i >= 0; i--) \
43 #define RSWITCH_TOP_OFFSET 0x00008000
44 #define RSWITCH_COMA_OFFSET 0x00009000
45 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */
46 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */
47 #define RSWITCH_GWCA0_OFFSET 0x00010000
48 #define RSWITCH_GWCA1_OFFSET 0x00012000
54 #define GWCA_INDEX 0
56 #define GWCA_IPV_NUM 0
[all …]
/openbmc/linux/include/linux/
H A Dpci_ids.h15 #define PCI_CLASS_NOT_DEFINED 0x0000
16 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
18 #define PCI_BASE_CLASS_STORAGE 0x01
19 #define PCI_CLASS_STORAGE_SCSI 0x0100
20 #define PCI_CLASS_STORAGE_IDE 0x0101
21 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
22 #define PCI_CLASS_STORAGE_IPI 0x0103
23 #define PCI_CLASS_STORAGE_RAID 0x0104
24 #define PCI_CLASS_STORAGE_SATA 0x0106
25 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
[all …]
/openbmc/u-boot/include/
H A Dpci_ids.h12 #define PCI_CLASS_NOT_DEFINED 0x0000
13 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
15 #define PCI_BASE_CLASS_STORAGE 0x01
16 #define PCI_CLASS_STORAGE_SCSI 0x0100
17 #define PCI_CLASS_STORAGE_IDE 0x0101
18 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
19 #define PCI_CLASS_STORAGE_IPI 0x0103
20 #define PCI_CLASS_STORAGE_RAID 0x0104
21 #define PCI_CLASS_STORAGE_SATA 0x0106
22 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.h15 #define ID_REV (0x00)
16 #define ID_REV_ID_MASK_ (0xFFFF0000)
17 #define ID_REV_ID_LAN7430_ (0x74300000)
18 #define ID_REV_ID_LAN7431_ (0x74310000)
19 #define ID_REV_ID_LAN743X_ (0x74300000)
20 #define ID_REV_ID_A011_ (0xA0110000) // PCI11010
21 #define ID_REV_ID_A041_ (0xA0410000) // PCI11414
22 #define ID_REV_ID_A0X1_ (0xA0010000)
24 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
25 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))
[all …]

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