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/openbmc/linux/drivers/net/ipa/reg/
H A Dgsi_reg-v5.0.c12 0x0000c01c + 0x1000 * GSI_EE_AP);
15 0x0000c028 + 0x1000 * GSI_EE_AP);
18 [CHTYPE_PROTOCOL] = GENMASK(6, 0),
27 0x00014000 + 0x12000 * GSI_EE_AP, 0x80);
30 [CH_R_LENGTH] = GENMASK(23, 0),
35 0x00014004 + 0x12000 * GSI_EE_AP, 0x80);
37 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x00014008 + 0x12000 * GSI_EE_AP, 0x80);
39 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001400c + 0x12000 * GSI_EE_AP, 0x80);
42 [WRR_WEIGHT] = GENMASK(3, 0),
54 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x00014048 + 0x12000 * GSI_EE_AP, 0x80);
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dlpasscc-sdm845.c19 .halt_reg = 0x12000,
22 .enable_reg = 0x12000,
23 .enable_mask = BIT(0),
32 .halt_reg = 0x1f000,
35 .enable_reg = 0x1f000,
36 .enable_mask = BIT(0),
45 .halt_reg = 0x20,
49 .enable_reg = 0x20,
50 .enable_mask = BIT(0),
59 .halt_reg = 0x38,
[all …]
H A Dlpasscc-sc8280xp.c21 [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
22 [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
23 [LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 },
31 .max_register = 0x1000,
41 [LPASS_AUDIO_SWR_TX_CGCR] = { 0xc010, 1 },
49 .max_register = 0x12000,
74 return qcom_cc_probe_by_index(pdev, 0, desc); in lpasscc_sc8280xp_probe()
/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_dp501.c34 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_ack()
35 sendack |= 0x80; in send_ack()
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_ack()
42 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_nack()
43 sendack &= ~0x80; in send_nack()
44 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_nack()
50 u32 retry = 0; in wait_ack()
52 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); in wait_ack()
53 waitack &= 0x80; in wait_ack()
66 u32 retry = 0; in wait_nack()
[all …]
/openbmc/linux/arch/arm/mach-dove/
H A Ddove.h14 * e0000000 @runtime 128M PCIe-0 Memory space
18 * f2000000 fee00000 1M PCIe-0 I/O space
22 #define DOVE_CESA_PHYS_BASE 0xc8000000
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
26 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
29 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
32 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
35 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
39 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4350.dtsi18 cpu@0 {
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
/openbmc/qemu/tests/qemu-iotests/
H A D04625 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
60 local pattern=0
61 local cur_sec=0
63 for ((i=0;i<=$((sectors - 1));i++)); do
71 backing_io 0 32 write | $QEMU_IO "$TEST_IMG" | _filter_qemu_io
84 aio_write -P 10 0x18000 0x2000
87 aio_write -P 11 0x12000 0x2000
88 aio_write -P 12 0x1c000 0x2000
98 aio_write -P 20 0x28000 0x2000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sc8280xp-lpasscc.yaml47 reg = <0x032a9000 0x1000>;
56 reg = <0x033e0000 0x12000>;
/openbmc/u-boot/arch/arm/mach-orion5x/include/mach/
H A Dorion5x.h22 #define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500))
23 #define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000))
24 #define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000))
25 #define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))
26 #define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000))
27 #define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100))
28 #define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000))
29 #define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100))
30 #define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300))
31 #define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000))
[all …]
/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dsoc.h16 #define INTREG_BASE 0xd0000000
18 #define KW_OFFSET_REG (INTREG_BASE + 0x20080)
21 #define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
22 #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
24 #define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500))
25 #define KW_TWSI_BASE (KW_REGISTER(0x11000))
26 #define KW_UART0_BASE (KW_REGISTER(0x12000))
27 #define KW_UART1_BASE (KW_REGISTER(0x12100))
28 #define KW_MPP_BASE (KW_REGISTER(0x10000))
29 #define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100))
[all …]
/openbmc/linux/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dmvebu-uart.txt39 reg = <0x12000 0x18>;
40 clocks = <&uartclk 0>;
50 reg = <0x12200 0x30>;
/openbmc/linux/drivers/media/platform/qcom/venus/
H A Dhfi_venus_io.h9 #define VBIF_BASE 0x80000
11 #define VBIF_AXI_HALT_CTRL0 0x208
12 #define VBIF_AXI_HALT_CTRL1 0x20c
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
18 #define CPU_BASE 0xc0000
20 #define CPU_CS_BASE (CPU_BASE + 0x12000)
21 #define CPU_IC_BASE (CPU_BASE + 0x1f000)
22 #define CPU_BASE_V6 0xa0000
24 #define CPU_IC_BASE_V6 (CPU_BASE_V6 + 0x138)
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm63146.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
75 #clock-cells = <0>;
89 ranges = <0x0 0x0 0x81000000 0x8000>;
95 reg = <0x1000 0x1000>,
96 <0x2000 0x2000>,
[all …]
H A Dbcm63158.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
39 reg = <0x0 0x2>;
47 reg = <0x0 0x3>;
80 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
108 ranges = <0x0 0x0 0x81000000 0x8000>;
[all …]
H A Dbcm6813.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
39 reg = <0x0 0x2>;
47 reg = <0x0 0x3>;
80 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
108 ranges = <0x0 0x0 0x81000000 0x8000>;
[all …]
H A Dbcm4912.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
39 reg = <0x0 0x2>;
47 reg = <0x0 0x3>;
80 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
108 ranges = <0x0 0x0 0x81000000 0x8000>;
[all …]
/openbmc/linux/drivers/reset/
H A Dreset-qcom-aoss.c30 [AOSS_CC_MSS_RESTART] = {0x10000},
31 [AOSS_CC_CAMSS_RESTART] = {0x11000},
32 [AOSS_CC_VENUS_RESTART] = {0x12000},
33 [AOSS_CC_GPU_RESTART] = {0x13000},
34 [AOSS_CC_DISPSS_RESTART] = {0x14000},
35 [AOSS_CC_WCSS_RESTART] = {0x20000},
36 [AOSS_CC_LPASS_RESTART] = {0x30000},
59 return 0; in qcom_aoss_control_assert()
68 writel(0, data->base + map->reg); in qcom_aoss_control_deassert()
71 return 0; in qcom_aoss_control_deassert()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h12 #define REGS_AHB0_BASE 0x01C00000
13 #define REGS_AHB1_BASE 0x00800000
14 #define REGS_AHB2_BASE 0x03000000
15 #define REGS_APB0_BASE 0x06000000
16 #define REGS_APB1_BASE 0x07000000
17 #define REGS_RCPUS_BASE 0x08000000
19 #define SUNXI_SRAM_D_BASE 0x08100000
22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm63178.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
86 #clock-cells = <0>;
100 ranges = <0 0x81000000 0x8000>;
107 reg = <0x1000 0x1000>,
[all …]
H A Dbcm6878.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
76 #clock-cells = <0>;
90 ranges = <0 0x81000000 0x8000>;
96 reg = <0x1000 0x1000>,
97 <0x2000 0x2000>,
[all …]
H A Dbcm6855.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
85 #clock-cells = <0>;
99 ranges = <0 0x81000000 0x8000>;
106 reg = <0x1000 0x1000>,
[all …]
H A Dbcm47622.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
47 reg = <0x3>;
81 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
109 ranges = <0 0x81000000 0x8000>;
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/openbmc/linux/arch/mips/include/asm/sn/sn0/
H A Dkldir.h28 * 0x2000000 (32M) +-----------------------------------------+
30 * 0x1F80000 (31.5M) +-----------------------------------------+
32 * 0x1C00000 (30M) +-----------------------------------------+
34 * 0x0800000 (28M) +-----------------------------------------+
36 * 0x1B00000 (27M) +-----------------------------------------+
38 * 0x1A00000 (26M) +-----------------------------------------+
40 * 0x1800000 (24M) +-----------------------------------------+
42 * 0x1600000 (22M) +-----------------------------------------+
48 * 0x190000 (2M--) +-----------------------------------------+
51 * 0x34000 (208K) +-----------------------------------------+
[all …]

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